[PATCH] D156345: RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG
Arthur Eubanks via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 2 14:16:44 PDT 2023
aeubanks added a comment.
also a slightly different assert running `llc` on the following
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%struct.BlockContext = type { [32 x i8], [32 x i8], [2 x [32 x i8]], [32 x i8], [32 x i8], [32 x i8], [32 x i8], [32 x i8], [2 x [32 x i8]], [2 x [32 x i8]], [32 x i8], [32 x i8], [32 x i8], [32 x i8], [16 x i8]
, [32 x i8], [32 x i8] }
%struct.CdfModeContext = type { [4 x [16 x i16]], [2 x [13 x [16 x i16]]], [9 x [16 x i16]], [5 x [4 x [16 x i16]]], [6 x [16 x i16]], [2 x [16 x i16]], [16 x i16], [2 x [13 x [8 x i16]]], [3 x [13 x [8 x i16]]]
, [8 x i16], [8 x [8 x i16]], [8 x i16], [8 x [8 x i16]], [3 x [8 x i16]], [2 x [7 x [8 x i16]]], [2 x [7 x [5 x [8 x i16]]]], [2 x [8 x [4 x i16]]], [4 x [3 x [4 x i16]]], [22 x [4 x i16]], [4 x i16], [5 x [4 x
i16]], [4 x [4 x i16]], [4 x i16], [2 x i16], [2 x i16], [7 x [2 x i16]], [7 x [2 x i16]], [4 x [2 x i16]], [22 x [2 x i16]], [6 x [2 x i16]], [2 x [2 x i16]], [6 x [2 x i16]], [3 x [2 x i16]], [4 x [2 x i16]],
[5 x [2 x i16]], [5 x [2 x i16]], [6 x [2 x i16]], [6 x [2 x i16]], [9 x [2 x i16]], [6 x [3 x [2 x i16]]], [3 x [3 x [2 x i16]]], [2 x [3 x [2 x i16]]], [3 x [3 x [2 x i16]]], [7 x [3 x [2 x i16]]], [3 x [2 x
i16]], [3 x [2 x i16]], [3 x [2 x i16]], [22 x [2 x i16]], [7 x [3 x [2 x i16]]], [2 x [2 x i16]], [2 x i16], [8 x i8] }
define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxprom, i1 %cmp54) #0 {
entry:
%0 = load i32, ptr null, align 8
br i1 %cmp54, label %if.end69, label %if.else
if.else: ; preds = %entry
%shr18 = and i32 %sub.i, 1
%idxprom.i = zext i32 %shr18 to i64
%arrayidx.i = getelementptr %struct.BlockContext, ptr null, i64 0, i32 14, i64 %idxprom.i
%1 = load i8, ptr %arrayidx.i, align 1
%conv.i = zext i8 %1 to i32
%and.i = and i32 %conv.i, 1
%2 = and i64 87960930222080, 1
%3 = inttoptr i64 %2 to ptr
%4 = load i32, ptr %3, align 4
%5 = and i64 %idxprom, 1
%6 = or i64 %5, 17592186044416
%7 = inttoptr i64 %6 to ptr
%8 = load i32, ptr %7, align 4
%9 = lshr i32 %bl, %sub.i
%10 = and i32 %9, 2
%11 = or i32 %bl, %10
%12 = select i1 %cmp54, i32 %8, i32 %4
%add.i = or i32 %_msprop1966, %and.i
%idxprom4 = zext i32 %bl to i64
%idxprom24 = zext i32 %add.i to i64
%13 = or i32 %0, 1
%14 = zext i32 %13 to i64
%.not2329 = icmp eq i32 %11, 0
%15 = select i1 %.not2329, i32 1, i32 %12
%arrayidx25 = getelementptr %struct.CdfModeContext, ptr null, i64 0, i32 3, i64 %idxprom4, i64 %idxprom24
store i64 %14, ptr null, align 8
store i32 %15, ptr %t, align 4
%call53 = tail call i32 null(ptr null, ptr %arrayidx25, i64 0)
%16 = xor i64 %idxprom, 1
%17 = inttoptr i64 %16 to ptr
%_msld1992 = load i32, ptr %17, align 8
%18 = icmp ne i32 %_msld1992, 0
%_msprop_icmp1993 = and i1 %18, false
br i1 %_msprop_icmp1993, label %19, label %20
19: ; preds = %if.else
unreachable
20: ; preds = %if.else
br i1 %cmp54, label %land.lhs.true56, label %if.end69
land.lhs.true56: ; preds = %20
ret i32 0
if.end69: ; preds = %20, %entry
%bx8.011941201 = phi i32 [ %shr18, %20 ], [ undef, %entry ]
store i32 %0, ptr null, align 8
%call79 = tail call fastcc i32 null(ptr %t, i32 0, i32 0, i32 0, i32 0)
%idxprom666 = zext i32 %bl to i64
%21 = xor i64 %idxprom666, 87960930222080
%idxprom675 = sext i32 %bx8.011941201 to i64
%arrayidx676 = getelementptr %struct.BlockContext, ptr null, i64 0, i32 14, i64 %idxprom675
%22 = inttoptr i64 %21 to ptr
%_msld1414 = load i8, ptr %22, align 1
store i8 %_msld1414, ptr %arrayidx676, align 1
ret i32 0
}
attributes #0 = { "frame-pointer"="all" "target-cpu"="x86-64" }
`clang: /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/CodeGen/InlineSpiller.cpp:1075: bool isRealSpill(const MachineInstr &): Assertion `Def.getNumOperands() == 1 && "Implicit def with more than one definition"' failed.`
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https://reviews.llvm.org/D156345/new/
https://reviews.llvm.org/D156345
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