[llvm] [AMDGPU] Allow shinking instruction with dead sdst (PR #68028)

via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 2 13:28:31 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 3dda1040d3fe56dbd8afd2eb823e891954de13f3 38d1bbe9ddc656356ab57ce7de1c788ab793e6f8 -- llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index bba533a4ca05..c39c8d1beb95 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -963,8 +963,8 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
       if (SDst) {
         // All of the instructions with carry outs also have an SGPR input in
         // src2.
-        const MachineOperand *Src2 = TII->getNamedOperand(MI,
-                                                          AMDGPU::OpName::src2);
+        const MachineOperand *Src2 =
+            TII->getNamedOperand(MI, AMDGPU::OpName::src2);
 
         // We can shrink the instruction right now if sdst is dead anyway and
         // carry-in is not a register. If it is a register then VOP2 form shall

``````````

</details>


https://github.com/llvm/llvm-project/pull/68028


More information about the llvm-commits mailing list