[llvm] d4fb503 - CodeGen: Add regressions from subreg_to_reg implicit-defs
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 2 12:38:39 PDT 2023
Author: Matt Arsenault
Date: 2023-10-02T22:38:31+03:00
New Revision: d4fb503f8330438a403a9be1d809cac53c01dab6
URL: https://github.com/llvm/llvm-project/commit/d4fb503f8330438a403a9be1d809cac53c01dab6
DIFF: https://github.com/llvm/llvm-project/commit/d4fb503f8330438a403a9be1d809cac53c01dab6.diff
LOG: CodeGen: Add regressions from subreg_to_reg implicit-defs
These catch assertions hit after 414ff812d6241b728754ce562081419e7fc091eb
Added:
llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
new file mode 100644
index 000000000000000..73b180dc4ae765f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
@@ -0,0 +1,187 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
+
+; Check there's no assert in spilling from implicit-def operands on an
+; IMPLICIT_DEF.
+
+define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) {
+; CHECK-LABEL: widget:
+; CHECK: ; %bb.0: ; %bb
+; CHECK-NEXT: sub sp, sp, #144
+; CHECK-NEXT: stp x28, x27, [sp, #48] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x26, x25, [sp, #64] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x24, x23, [sp, #80] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x22, x21, [sp, #96] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x20, x19, [sp, #112] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #128] ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 144
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: .cfi_offset w19, -24
+; CHECK-NEXT: .cfi_offset w20, -32
+; CHECK-NEXT: .cfi_offset w21, -40
+; CHECK-NEXT: .cfi_offset w22, -48
+; CHECK-NEXT: .cfi_offset w23, -56
+; CHECK-NEXT: .cfi_offset w24, -64
+; CHECK-NEXT: .cfi_offset w25, -72
+; CHECK-NEXT: .cfi_offset w26, -80
+; CHECK-NEXT: .cfi_offset w27, -88
+; CHECK-NEXT: .cfi_offset w28, -96
+; CHECK-NEXT: mov w19, w6
+; CHECK-NEXT: mov w20, w5
+; CHECK-NEXT: mov x21, x4
+; CHECK-NEXT: mov x22, x3
+; CHECK-NEXT: mov x23, x2
+; CHECK-NEXT: mov w24, w1
+; CHECK-NEXT: mov w25, w0
+; CHECK-NEXT: mov w26, w1
+; CHECK-NEXT: Lloh0:
+; CHECK-NEXT: adrp x27, LJTI0_0 at PAGE
+; CHECK-NEXT: Lloh1:
+; CHECK-NEXT: add x27, x27, LJTI0_0 at PAGEOFF
+; CHECK-NEXT: mov w28, #1 ; =0x1
+; CHECK-NEXT: ; implicit-def: $w8
+; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Folded Spill
+; CHECK-NEXT: b LBB0_2
+; CHECK-NEXT: LBB0_1: ; %bb10
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: mov w0, w20
+; CHECK-NEXT: mov x1, x22
+; CHECK-NEXT: str wzr, [x21]
+; CHECK-NEXT: bl _putc
+; CHECK-NEXT: mov w0, w25
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: bl _putc
+; CHECK-NEXT: LBB0_2: ; %bb8
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: cmp w24, #39
+; CHECK-NEXT: b.hi LBB0_5
+; CHECK-NEXT: ; %bb.3: ; %bb8
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: adr x8, LBB0_1
+; CHECK-NEXT: ldrb w9, [x27, x26]
+; CHECK-NEXT: add x8, x8, x9, lsl #2
+; CHECK-NEXT: br x8
+; CHECK-NEXT: LBB0_4: ; %bb9
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: str w28, [x23]
+; CHECK-NEXT: b LBB0_2
+; CHECK-NEXT: LBB0_5: ; %bb8
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: cmp w24, #64
+; CHECK-NEXT: b.ne LBB0_2
+; CHECK-NEXT: b LBB0_9
+; CHECK-NEXT: LBB0_6: ; %bb13
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Folded Spill
+; CHECK-NEXT: tbz w19, #0, LBB0_2
+; CHECK-NEXT: ; %bb.7: ; %bb14
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: stp xzr, xzr, [sp]
+; CHECK-NEXT: stp x8, xzr, [sp, #16]
+; CHECK-NEXT: bl _fprintf
+; CHECK-NEXT: b LBB0_2
+; CHECK-NEXT: LBB0_8: ; %bb12
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: b LBB0_8
+; CHECK-NEXT: LBB0_9: ; %bb16
+; CHECK-NEXT: ldr x8, [sp, #40] ; 8-byte Folded Reload
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: ; kill: def $w8 killed $w8 killed $x8 def $x8
+; CHECK-NEXT: str x8, [sp]
+; CHECK-NEXT: bl _fprintf
+; CHECK-NEXT: brk #0x1
+; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
+; CHECK-NEXT: .cfi_endproc
+; CHECK-NEXT: .section __TEXT,__const
+; CHECK-NEXT: LJTI0_0:
+; CHECK-NEXT: .byte (LBB0_6-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_8-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_4-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_1-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
+; CHECK-NEXT: .byte (LBB0_1-LBB0_1)>>2
+bb:
+ br label %bb7
+
+bb7: ; preds = %bb14, %bb13, %bb
+ %phi = phi i32 [ poison, %bb ], [ %mul, %bb14 ], [ %mul, %bb13 ]
+ br label %bb8
+
+bb8: ; preds = %bb10, %bb9, %bb8, %bb7
+ switch i32 %arg1, label %bb8 [
+ i32 10, label %bb9
+ i32 64, label %bb16
+ i32 0, label %bb13
+ i32 39, label %bb10
+ i32 34, label %bb10
+ i32 1, label %bb12
+ ]
+
+bb9: ; preds = %bb8
+ store i32 1, ptr %arg2, align 4
+ br label %bb8
+
+bb10: ; preds = %bb8, %bb8
+ store i32 0, ptr %arg4, align 4
+ %call = tail call i32 @putc(i32 %arg5, ptr %arg3)
+ %call11 = tail call i32 @putc(i32 %arg, ptr null)
+ br label %bb8
+
+bb12: ; preds = %bb12, %bb8
+ br label %bb12
+
+bb13: ; preds = %bb8
+ %mul = mul i32 1, 1
+ br i1 %arg6, label %bb14, label %bb7
+
+bb14: ; preds = %bb13
+ %call15 = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, ptr null, i32 0, i32 %mul, ptr null)
+ br label %bb7
+
+bb16: ; preds = %bb8
+ %call17 = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, i32 %phi)
+ unreachable
+}
+
+declare i32 @fprintf(ptr, ptr, ...)
+declare i32 @putc(i32, ptr)
diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
new file mode 100644
index 000000000000000..66ba54f3e318e16
--- /dev/null
+++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; Check there's no assert in the coalescer from implicit-def operands
+; on an IMPLICIT_DEF.
+
+
+define i1 @_ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb(i32 %arg) {
+; CHECK-LABEL: _ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpl $1, %edi
+; CHECK-NEXT: je .LBB0_1
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: jne .LBB0_4
+; CHECK-NEXT: # %bb.3: # %if.end.i.i.preheader
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: movl $1, %ecx
+; CHECK-NEXT: .LBB0_4: # %if.then.i.i
+; CHECK-NEXT: movb $1, %dl
+; CHECK-NEXT: testb %dl, %dl
+; CHECK-NEXT: je .LBB0_6
+; CHECK-NEXT: .LBB0_7: # %do.end
+; CHECK-NEXT: movq %rcx, 0
+; CHECK-NEXT: movb %al, 0
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: testb %dl, %dl
+; CHECK-NEXT: jne .LBB0_7
+; CHECK-NEXT: .LBB0_6: # %if.then8
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+entry:
+ switch i32 %arg, label %if.then.i.i [
+ i32 1, label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
+ i32 0, label %if.end.i.i.preheader
+ ]
+
+if.end.i.i.preheader: ; preds = %entry
+ br label %if.then.i.i
+
+if.then.i.i: ; preds = %if.end.i.i.preheader, %entry
+ %i = phi i64 [ 0, %entry ], [ 1, %if.end.i.i.preheader ]
+ %i1 = phi i8 [ 0, %entry ], [ 1, %if.end.i.i.preheader ]
+ br label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
+
+"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit": ; preds = %if.then.i.i, %entry
+ %i2 = phi i64 [ 0, %entry ], [ %i, %if.then.i.i ]
+ %i3 = phi i8 [ 0, %entry ], [ %i1, %if.then.i.i ]
+ %i4 = phi i8 [ 0, %entry ], [ 1, %if.then.i.i ]
+ %tobool7.not = icmp eq i8 %i4, 0
+ br i1 %tobool7.not, label %if.then8, label %do.end
+
+if.then8: ; preds = %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
+ ret i1 false
+
+do.end: ; preds = %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
+ store i64 %i2, ptr null, align 8
+ store i8 %i3, ptr null, align 4
+ ret i1 false
+}
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