[PATCH] D156345: RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG

[Arthur Eubanks via Phabricator via llvm-commits]

aeubanks added a comment.

we're seeing crashes around RegisterCoalescer. I haven't bisected exactly which patch yet but I figured it's one of these patches

  $ cat /tmp/a.ll
  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
  target triple = "x86_64-unknown-linux-gnu"
  
  define i1 @_ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb(i32 %0) {
  entry:
    switch i32 %0, label %if.then.i.i [
      i32 1, label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
      i32 0, label %if.end.i.i.preheader
    ]
  
  if.end.i.i.preheader:                             ; preds = %entry
    br label %if.then.i.i
  
  if.then.i.i:                                      ; preds = %if.end.i.i.preheader, %entry
    %1 = phi i64 [ 0, %entry ], [ 1, %if.end.i.i.preheader ]
    %2 = phi i8 [ 0, %entry ], [ 1, %if.end.i.i.preheader ]
    br label %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
  
  "_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit": ; preds = %if.then.i.i, %entry
    %3 = phi i64 [ 0, %entry ], [ %1, %if.then.i.i ]
    %4 = phi i8 [ 0, %entry ], [ %2, %if.then.i.i ]
    %5 = phi i8 [ 0, %entry ], [ 1, %if.then.i.i ]
    %tobool7.not = icmp eq i8 %5, 0
    br i1 %tobool7.not, label %if.then8, label %do.end
  
  if.then8:                                         ; preds = %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
    ret i1 false
  
  do.end:                                           ; preds = %"_ZN4llvm8LLParser17parseMDFieldsImplIZNS0_17parseDIEnumeratorERPNS_6MDNodeEbE3$_0EEbT_RNS_5SMLocE.exit"
    store i64 %3, ptr null, align 8
    store i8 %4, ptr null, align 4
    ret i1 false
  }
  $ llc /tmp/a.ll
  llc: ../../llvm/lib/CodeGen/RegisterCoalescer.cpp:1443: bool (anonymous namespace)::RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &, MachineInstr *, bool &): Assertion `MO.getReg() == NewMI.getO
  perand(0).getReg() && MO.getSubReg() == 0' failed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156345/new/

https://reviews.llvm.org/D156345