[llvm] [RISCV][GlobalISel] Select G_PTR_ADD (PR #67605)

[Min-Yih Hsu via llvm-commits]

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@@ -245,6 +261,39 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   }
 }
 
+bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op,
+                                                 MachineIRBuilder &MIB,
+                                                 MachineRegisterInfo &MRI) {
+  assert(Op.isReg() && "Operand is not a register!");
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mshockwave wrote:

`getReg` will do the assertion of `isReg` so I don't think this is needed here.

https://github.com/llvm/llvm-project/pull/67605