[PATCH] D138551: [PowerPC] Mask constant operands in bit permutation calculation

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/pr59074.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64
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tingwang wrote:
> lkail wrote:
> > Any idea why it doesn't crash on `pwr8`?
> I think the DAGTypeLegalizer changed direction for this case on pwr8, for example:
> https://github.com/llvm/llvm-project/blob/d18523c0430cee513a07b5b2a89ad1adb43c91f1/llvm/lib/Target/PowerPC/PPCISelLowering.cpp#L1059
Yes, `-mcpu=pwr8` touches another codepath


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Comment at: llvm/test/CodeGen/PowerPC/pr59074.ll:103
+entry:
+  %v1 = load <2 x i128>, <2 x i128>* %0
+  %v2 = insertelement <2 x i128> %v1, i128 12, i32 0
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lkail wrote:
> Any idea why it doesn't crash for scalars?
We can't write `shl i64 %a, 65` to reproduce it, because such simple pattern will be converted to poison value by combiner.

The crash is actually from `srl_parts a, b, 0` in SDAG, which then legalizes into a group of `PPCISD::SHL/SRL a, b, 0/64/-64`.

Legalizer splits `2xi128` into two `1xi128`, during the process some `sub a, a` is generated and consumed by `srl_parts` as shift amounts. This may expose some limitations of the combiner.


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  https://reviews.llvm.org/D138551/new/

https://reviews.llvm.org/D138551