[PATCH] D138551: [PowerPC] Mask constant operands in bit permutation calculation

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1487
+        // sld takes 7 bits, slw takes 6.
+        unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1);
 
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tingwang wrote:
> If I understand correctly, `ShiftAmt` is unsigned so a "negative value" means very large shift amount here. Can we simply cap `ShiftAmt` to be no larger than `NumBits`, and then seems additional boundary checks are not necessary?
Although LLVM langref says when shift amount is larger than number bits, here the `case` also matches for `PPCISD::SHL`, which fully conforms to behavior of Power's shift instructions (`sld`, for example):

`sld r3, r3, r4` when r4=`0b110111111` or `0b0000111111` the result is the same (the instruction only cares about lowest 7 bits).


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  https://reviews.llvm.org/D138551/new/

https://reviews.llvm.org/D138551