[llvm] [RISCV] Improve constant materialization by using a sequence that end… (PR #66943)

[Craig Topper via llvm-commits]

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@@ -206,10 +206,25 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   assert(ActiveFeatures[RISCV::Feature64Bit] &&
          "Expected RV32 to only need 2 instructions");
 
+  // If the lower 13 bits are something like 0x17ff, try to turn it into 0x1800
+  // and use a final addi to correct it back to 0x17ff. This will create a
+  // sequence ending in 2 addis.
+  if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
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topperc wrote:

This statement from my response "it looked like what I wanted to do was make bit 12 and 13 to both be set so that the lower bits were at least the start of a simm12." was refering to the change done by this line `AdjustedVal = Val - Imm12`. We want `AdjustedVal` to have bits 13 and 12 set so that when we call `generateInstSeqImpl` on `AdjustedVal`, it will subtract a simm12 of 0xfffffffffffff800 and create more than 12 trailing zeros for the next recursive call to `generateInstSeqImpl`.

https://github.com/llvm/llvm-project/pull/66943