[llvm] [RISCV] Improve constant materialization by using a sequence that end… (PR #66943)

[Philip Reames via llvm-commits]

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@@ -206,10 +206,25 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   assert(ActiveFeatures[RISCV::Feature64Bit] &&
          "Expected RV32 to only need 2 instructions");
 
+  // If the lower 13 bits are something like 0x17ff, try to turn it into 0x1800
+  // and use a final addi to correct it back to 0x17ff. This will create a
+  // sequence ending in 2 addis.
+  if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
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preames wrote:

I'm suspecting a typo here.  I can't line your words up with the code.

Specifically, this check: (Val & 0x1800) == 0x1000).  This is checking that the 13-th bit is *set*, and the 12th bit is *not set*.  This seems to differ from your response where you say that you're making sure both 12 and 13 *are* set.  If you were comparing to 0x1800 (not 0x1000) that would be the effect.  

However, the line int64_t Imm12 = -(0x800 - (Val & 0xfff)); requires bit 12 of Val to be clear to produce a uint11_t which can then be inverted into a sint12_t without cornercases.  So maybe it's the code that's correct and your comment that is off?


https://github.com/llvm/llvm-project/pull/66943