[PATCH] D156985: [AMDGPU] Remove the support for non-True16 copies between different register sizes.

[Ivan Kosarev via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG287f6cdd17cd: [AMDGPU] Remove the support for non-True16 copies between different register… (authored by kosarev).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156985/new/

https://reviews.llvm.org/D156985

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir


Index: llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir
+++ /dev/null
@@ -1,36 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos -amdgpu-fix-16-bit-physreg-copies -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-
-# GCN-LABEL: name: lo16_to_v32
-# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
-name: lo16_to_v32
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr1_lo16 = COPY $vgpr0
-    S_ENDPGM 0
-...
-
-# GCN-LABEL: name: v32_to_lo16
-# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
-name: v32_to_lo16
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr1 = COPY $vgpr0_lo16
-    S_ENDPGM 0
-...
-
-# GCN-LABEL: name: samereg
-# GCN:      $vgpr0 = IMPLICIT_DEF
-# GCN-NEXT: BUNDLE
-# GCN-NEXT: S_ENDPGM
-name: samereg
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr0 = COPY $vgpr0_lo16
-    S_ENDPGM 0
-...
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -733,18 +733,11 @@
   // we remove Fix16BitCopies and this code block?
   if (Fix16BitCopies) {
     if (((Size == 16) != (SrcSize == 16))) {
-      if (ST.hasTrue16BitInsts()) {
-        // Non-VGPR Src and Dst will later be expanded back to 32 bits.
-        MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
-        MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
-        RegToFix = SubReg;
-      } else {
-        MCRegister &RegToFix = (Size == 16) ? DestReg : SrcReg;
-        MCRegister Super = RI.get32BitRegister(RegToFix);
-        assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix ||
-               RI.getSubReg(Super, AMDGPU::hi16) == RegToFix);
-        RegToFix = Super;
-      }
+      // Non-VGPR Src and Dst will later be expanded back to 32 bits.
+      assert(ST.hasTrue16BitInsts());
+      MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
+      MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
+      RegToFix = SubReg;
 
       if (DestReg == SrcReg) {
         // Identity copy. Insert empty bundle since ExpandPostRA expects an


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