[llvm] 287f6cd - [AMDGPU] Remove the support for non-True16 copies between different register sizes.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2023-09-26T14:46:34+01:00
New Revision: 287f6cdd17cdef06bb483d444b7d1f4a18fff43d

URL: https://github.com/llvm/llvm-project/commit/287f6cdd17cdef06bb483d444b7d1f4a18fff43d
DIFF: https://github.com/llvm/llvm-project/commit/287f6cdd17cdef06bb483d444b7d1f4a18fff43d.diff

LOG: [AMDGPU] Remove the support for non-True16 copies between different register sizes.

Differential Revision: https://reviews.llvm.org/D156985

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 30e3179f8eb7d83..e8bd73a220701e3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -733,18 +733,11 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   // we remove Fix16BitCopies and this code block?
   if (Fix16BitCopies) {
     if (((Size == 16) != (SrcSize == 16))) {
-      if (ST.hasTrue16BitInsts()) {
-        // Non-VGPR Src and Dst will later be expanded back to 32 bits.
-        MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
-        MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
-        RegToFix = SubReg;
-      } else {
-        MCRegister &RegToFix = (Size == 16) ? DestReg : SrcReg;
-        MCRegister Super = RI.get32BitRegister(RegToFix);
-        assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix ||
-               RI.getSubReg(Super, AMDGPU::hi16) == RegToFix);
-        RegToFix = Super;
-      }
+      // Non-VGPR Src and Dst will later be expanded back to 32 bits.
+      assert(ST.hasTrue16BitInsts());
+      MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
+      MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
+      RegToFix = SubReg;
 
       if (DestReg == SrcReg) {
         // Identity copy. Insert empty bundle since ExpandPostRA expects an

diff  --git a/llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir b/llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir
deleted file mode 100644
index 074f5de9224e69f..000000000000000
--- a/llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir
+++ /dev/null
@@ -1,36 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos -amdgpu-fix-16-bit-physreg-copies -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-
-# GCN-LABEL: name: lo16_to_v32
-# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
-name: lo16_to_v32
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr1_lo16 = COPY $vgpr0
-    S_ENDPGM 0
-...
-
-# GCN-LABEL: name: v32_to_lo16
-# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
-name: v32_to_lo16
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr1 = COPY $vgpr0_lo16
-    S_ENDPGM 0
-...
-
-# GCN-LABEL: name: samereg
-# GCN:      $vgpr0 = IMPLICIT_DEF
-# GCN-NEXT: BUNDLE
-# GCN-NEXT: S_ENDPGM
-name: samereg
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    $vgpr0 = IMPLICIT_DEF
-    $vgpr0 = COPY $vgpr0_lo16
-    S_ENDPGM 0
-...