[llvm] [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (PR #67359)

[Craig Topper via llvm-commits]

================
@@ -363,6 +366,32 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
   return true;
 }
 
+bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
+                                               MachineIRBuilder &MIB) const {
+  if (!STI.isRV64())
+    return false;
+
+  const MachineOperand &Size = MI.getOperand(2);
+  // Only Size == 32 (i.e. shift by 32 bits) is acceptable at this point.
+  if (!Size.isImm() || Size.getImm() != 32)
+    return false;
+
+  const MachineOperand &Src = MI.getOperand(1);
+  const MachineOperand &Dst = MI.getOperand(0);
+  assert(Src.isReg() && Dst.isReg());
+  // addiw rd, rs, 0 (i.e. sext.w rd, rs)
+  MachineInstr *NewMI = MIB.buildInstr(RISCV::ADDIW)
----------------
topperc wrote:

I think you can do `MIB.buildInstr(RISCV::ADDIW, {MI.getOperand(0)},  {MI.getOperand(1)}).addImm(0U);` This should automatically call getReg on the operand. I only learned this last week.

https://github.com/llvm/llvm-project/pull/67359