[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 11 09:54:00 PDT 2023


RKSimon planned changes to this revision.
RKSimon added a comment.

Still a few more regressions to address - I'll be back :)



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Comment at: llvm/test/CodeGen/X86/pr22970.ll:18-19
 ; X64-NEXT:    andl $4095, %esi # imm = 0xFFF
-; X64-NEXT:    movl 32(%rdi,%rsi,4), %eax
+; X64-NEXT:    leal 32(,%rsi,4), %eax
+; X64-NEXT:    movl (%rdi,%rax), %eax
 ; X64-NEXT:    retq
----------------
pengfei wrote:
> Regression?
Yes, I missed these - it looks like we're losing NSW/NUW flags on the ADD when it gets truncated.


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Comment at: llvm/test/CodeGen/X86/pr38217.ll:32-34
+; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%r9), %r9d
 ; CHECK-NEXT:    movw %r9w, -1(%r11)
+; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%rax), %eax
----------------
pengfei wrote:
> Looks like regression?
Similar issue - we lose the NUW flag on the shl(x,1) on truncation and value tracking can't recover later on. 


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Comment at: llvm/test/CodeGen/X86/shift-combine.ll:106
 ; X64-NEXT:    subl %edi, %esi
-; X64-NEXT:    shrl $3, %esi
-; X64-NEXT:    leaq (%rdx,%rsi,4), %rax
+; X64-NEXT:    shrl %esi
+; X64-NEXT:    leaq (%rsi,%rdx), %rax
----------------
pengfei wrote:
> Will `addl %esi, %esi` better?
lshr not shl


================
Comment at: llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll:258-279
+; SSE2-NEXT:    movzwl -24(%rsp,%r10,2), %r10d
+; SSE2-NEXT:    movd %r10d, %xmm0
 ; SSE2-NEXT:    movzwl -24(%rsp,%rax,2), %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-NEXT:    movzwl -24(%rsp,%r9,2), %eax
+; SSE2-NEXT:    movd %eax, %xmm0
----------------
pengfei wrote:
> The change is not easy for manually check, but actually doesn't do any change expect for the register order. It would be better if we can avoid to generate such difference.
I'll see if I can isolate the change - I'm not certain if its something to do with LowerBUILD_VECTORAsVariablePermute or something more generic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472



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