[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/test/CodeGen/X86/lea-opt2.ll:196-197
+; CHECK-NEXT:    shll $12, %ecx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    andq $-4096, %rcx # imm = 0xF000
 ; CHECK-NEXT:    addq %rcx, %rdi
----------------
There can also change to 32-bit instructions, maybe improve in the future.


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Comment at: llvm/test/CodeGen/X86/pr22970.ll:18-19
 ; X64-NEXT:    andl $4095, %esi # imm = 0xFFF
-; X64-NEXT:    movl 32(%rdi,%rsi,4), %eax
+; X64-NEXT:    leal 32(,%rsi,4), %eax
+; X64-NEXT:    movl (%rdi,%rax), %eax
 ; X64-NEXT:    retq
----------------
Regression?


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Comment at: llvm/test/CodeGen/X86/pr22970.ll:41-42
 ; X64-NEXT:    andl $4095, %esi # imm = 0xFFF
-; X64-NEXT:    movl 32(%rdi,%rsi,4), %eax
+; X64-NEXT:    leal 32(,%rsi,4), %eax
+; X64-NEXT:    movl (%rdi,%rax), %eax
 ; X64-NEXT:    retq
----------------
ditto.


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Comment at: llvm/test/CodeGen/X86/pr38217.ll:32-34
+; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%r9), %r9d
 ; CHECK-NEXT:    movw %r9w, -1(%r11)
+; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%rax), %eax
----------------
Looks like regression?


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Comment at: llvm/test/CodeGen/X86/shift-combine.ll:106
 ; X64-NEXT:    subl %edi, %esi
-; X64-NEXT:    shrl $3, %esi
-; X64-NEXT:    leaq (%rdx,%rsi,4), %rax
+; X64-NEXT:    shrl %esi
+; X64-NEXT:    leaq (%rsi,%rdx), %rax
----------------
Will `addl %esi, %esi` better?


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Comment at: llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll:258-279
+; SSE2-NEXT:    movzwl -24(%rsp,%r10,2), %r10d
+; SSE2-NEXT:    movd %r10d, %xmm0
 ; SSE2-NEXT:    movzwl -24(%rsp,%rax,2), %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-NEXT:    movzwl -24(%rsp,%r9,2), %eax
+; SSE2-NEXT:    movd %eax, %xmm0
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The change is not easy for manually check, but actually doesn't do any change expect for the register order. It would be better if we can avoid to generate such difference.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472