[llvm] [GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT (PR #65830)

[Amara Emerson via llvm-commits]

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@@ -718,8 +718,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
       .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
-      .clampMinNumElements(0, s16, 4)
-      .clampMaxNumElements(0, s16, 8);
+      .minScalarOrEltIf(
+          [=](const LegalityQuery &Query) { return Query.Types[0] == v2s16; },
+          0, s32);
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aemerson wrote:

When I meant the type index, I meant the `0` in `0, s32);`

https://github.com/llvm/llvm-project/pull/65830