[llvm] [GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT (PR #65830)

[via llvm-commits]

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@@ -155,3 +155,15 @@ bb:
   store i64 %tmp4, ptr %p
   ret i64 %out
 }
+
+define <2 x i16> @pr63826(<2 x i16> %vec) {
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vfdff wrote:

Oh, I didn't find the most appropriate file to add this use case, but this file name has a **insert** postfix, so I'm pleasure to move this case to another more appropriate  file. do you have some suggestion?
Anyhow, I just want a case show the **gloabl ISel** and **DAG Isel** have same output assemble.

https://github.com/llvm/llvm-project/pull/65830