[llvm] [AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP (PR #65897)

[Amara Emerson via llvm-commits]

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@@ -338,6 +338,50 @@ void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI,
   Store.eraseFromParent();
 }
 
+bool matchOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
+                  std::tuple<Register, Register, Register> &MatchInfo) {
+  const LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+  if (!DstTy.isVector())
+    return false;
+
+  MachineInstr *LHS =
+      getOpcodeDef(TargetOpcode::G_AND, MI.getOperand(1).getReg(), MRI);
+  MachineInstr *RHS =
+      getOpcodeDef(TargetOpcode::G_AND, MI.getOperand(2).getReg(), MRI);
+  if (!LHS || !RHS)
+    return false;
+
+  auto *BV1 = getOpcodeDef<GBuildVector>(LHS->getOperand(2).getReg(), MRI);
+  auto *BV2 = getOpcodeDef<GBuildVector>(RHS->getOperand(2).getReg(), MRI);
+  if (!BV1 || !BV2)
+    return false;
+
+  for (int k = 0; k < DstTy.getNumElements(); k++) {
+    auto ValAndVReg1 = getIConstantVRegValWithLookThrough(
+        BV1->getOperand(k + 1).getReg(), MRI);
+    auto ValAndVReg2 = getIConstantVRegValWithLookThrough(
+        BV2->getOperand(k + 1).getReg(), MRI);
+    if (!ValAndVReg1 || !ValAndVReg2 ||
+        ValAndVReg1->Value != ~ValAndVReg2->Value)
+      return false;
+  }
+
+  std::get<0>(MatchInfo) = LHS->getOperand(1).getReg();
+  std::get<1>(MatchInfo) = RHS->getOperand(1).getReg();
+  std::get<2>(MatchInfo) = RHS->getOperand(2).getReg();
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aemerson wrote:

I think you can just do `MatchInfo = {v1,v2,v3};`

https://github.com/llvm/llvm-project/pull/65897