[llvm] [ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM (PR #65849)

[via llvm-commits]

https://github.com/vfdff created https://github.com/llvm/llvm-project/pull/65849:

Set ISD::FMINNUM/FMAXNUM legal when feature HasV8 is enable.

Fixes https://github.com/llvm/llvm-project/issues/65820

>From a6772a0aacf3a6769a316c1d4b59b63044fe03e8 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Sat, 9 Sep 2023 07:27:20 -0400
Subject: [PATCH] [ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM

Set ISD::FMINNUM/FMAXNUM legal when feature HasV8 is set.

Fixes https://github.com/llvm/llvm-project/issues/65820
---
 llvm/lib/Target/ARM/ARMISelLowering.cpp       |  2 +-
 .../CodeGen/ARM/minnum-maxnum-intrinsics.ll   | 42 +++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 80a1476660947e0..c483f52f5186388 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1504,7 +1504,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FRINT, MVT::f32, Legal);
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
     setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
-    if (Subtarget->hasNEON()) {
+    if (Subtarget->hasNEON() && Subtarget->hasV8Ops()) {
       setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
       setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
       setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index e17075d067c26bd..6d17faadd3d4ff7 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -1456,3 +1456,45 @@ define <2 x double> @fmaxnumv264_non_zero_intrinsic(<2 x double> %x) {
   %a = call nnan <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double><double 1.0, double 1.0>)
   ret <2 x double> %a
 }
+
+define void @pr65820(ptr %y, <4 x float> %splat) {
+; ARMV7-LABEL: pr65820:
+; ARMV7:       @ %bb.0: @ %entry
+; ARMV7-NEXT:    vmov d16, r2, r3
+; ARMV7-NEXT:    vdup.32 q8, d16[0]
+; ARMV7-NEXT:    vcgt.f32 q9, q8, #0
+; ARMV7-NEXT:    vand q8, q8, q9
+; ARMV7-NEXT:    vst1.32 {d16, d17}, [r0]
+; ARMV7-NEXT:    bx lr
+;
+; ARMV8-LABEL: pr65820:
+; ARMV8:       @ %bb.0: @ %entry
+; ARMV8-NEXT:    vldr s0, .LCPI33_0
+; ARMV8-NEXT:    vmov s2, r2
+; ARMV8-NEXT:    vmaxnm.f32 s0, s2, s0
+; ARMV8-NEXT:    vstr s0, [r0]
+; ARMV8-NEXT:    vstr s0, [r0, #4]
+; ARMV8-NEXT:    vstr s0, [r0, #8]
+; ARMV8-NEXT:    vstr s0, [r0, #12]
+; ARMV8-NEXT:    mov pc, lr
+; ARMV8-NEXT:    .p2align 2
+; ARMV8-NEXT:  @ %bb.1:
+; ARMV8-NEXT:  .LCPI33_0:
+; ARMV8-NEXT:    .long 0x00000000 @ float 0
+;
+; ARMV8M-LABEL: pr65820:
+; ARMV8M:       @ %bb.0: @ %entry
+; ARMV8M-NEXT:    vmov d0, r2, r3
+; ARMV8M-NEXT:    vmov r1, s0
+; ARMV8M-NEXT:    vmov.i32 q0, #0x0
+; ARMV8M-NEXT:    vdup.32 q1, r1
+; ARMV8M-NEXT:    vmaxnm.f32 q0, q1, q0
+; ARMV8M-NEXT:    vstrw.32 q0, [r0]
+; ARMV8M-NEXT:    bx lr
+entry:
+  %broadcast.splat = shufflevector <4 x float> %splat, <4 x float> zeroinitializer, <4 x i32> zeroinitializer
+  %0 = fcmp ogt <4 x float> %broadcast.splat, zeroinitializer
+  %1 = select <4 x i1> %0, <4 x float> %broadcast.splat, <4 x float> zeroinitializer
+  store <4 x float> %1, ptr %y, align 4
+  ret void
+}