[llvm] f2b0443 - [ARM] Correct Cortex-M55 scheduling info for VMINV/VMAXV
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 8 10:15:27 PDT 2023
Author: David Green
Date: 2023-09-08T18:15:22+01:00
New Revision: f2b04434fc49e41444d1a1a4065e8fbe249538c2
URL: https://github.com/llvm/llvm-project/commit/f2b04434fc49e41444d1a1a4065e8fbe249538c2
DIFF: https://github.com/llvm/llvm-project/commit/f2b04434fc49e41444d1a1a4065e8fbe249538c2.diff
LOG: [ARM] Correct Cortex-M55 scheduling info for VMINV/VMAXV
It appears that these were the wrong way around, with the wrong type sizes
taking extra cycles. The smaller i8 sizes are now the ones marked as taking
longer.
Added:
Modified:
llvm/lib/Target/ARM/ARMScheduleM55.td
llvm/test/tools/llvm-mca/ARM/m55-mve-int.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMScheduleM55.td b/llvm/lib/Target/ARM/ARMScheduleM55.td
index 35724703b4c3229..ff05936e8ba45c4 100644
--- a/llvm/lib/Target/ARM/ARMScheduleM55.td
+++ b/llvm/lib/Target/ARM/ARMScheduleM55.td
@@ -353,9 +353,9 @@ def : InstRW<[M55Write2IntE2], (instregex "MVE_VHADD")>;
def : InstRW<[M55Write2IntE2], (instregex "MVE_VHCADD")>;
def : InstRW<[M55Write2IntE2], (instregex "MVE_VHSUB")>;
def : InstRW<[M55Write2IntE2], (instregex "MVE_V(MAX|MIN)A?(s|u)")>;
-def : InstRW<[M55Write2IntE3], (instregex "MVE_V(MAX|MIN)A?V(s|u)8")>;
+def : InstRW<[M55Write2IntE3Plus2], (instregex "MVE_V(MAX|MIN)A?V(s|u)8")>;
def : InstRW<[M55Write2IntE3Plus1], (instregex "MVE_V(MAX|MIN)A?V(s|u)16")>;
-def : InstRW<[M55Write2IntE3Plus2], (instregex "MVE_V(MAX|MIN)A?V(s|u)32")>;
+def : InstRW<[M55Write2IntE3], (instregex "MVE_V(MAX|MIN)A?V(s|u)32")>;
def : InstRW<[M55Write2IntE4NoFwd], (instregex "MVE_VMOVN")>;
def : InstRW<[M55Write2IntE2], (instregex "MVE_VMOVL")>;
def : InstRW<[M55Write2IntE3], (instregex "MVE_VMULL[BT]p")>;
diff --git a/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s b/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s
index dc8025ea5fc255a..c2b827fe81534e7 100644
--- a/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s
@@ -631,15 +631,15 @@ vsub.i32 q0, q2, r0
# CHECK-NEXT: 1 1 2.00 vmaxa.s8 q0, q2
# CHECK-NEXT: 1 1 2.00 vmaxa.s16 q0, q2
# CHECK-NEXT: 1 1 2.00 vmaxa.s32 q0, q2
-# CHECK-NEXT: 1 2 2.00 vmaxv.s8 r0, q2
-# CHECK-NEXT: 1 2 2.00 vmaxv.u8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.u8 r0, q2
# CHECK-NEXT: 1 3 2.00 vmaxv.s16 r0, q2
# CHECK-NEXT: 1 3 2.00 vmaxv.u16 r0, q2
-# CHECK-NEXT: 1 4 2.00 vmaxv.s32 r0, q2
-# CHECK-NEXT: 1 4 2.00 vmaxv.u32 r0, q2
-# CHECK-NEXT: 1 2 2.00 vmaxav.s8 r0, q2
+# CHECK-NEXT: 1 2 2.00 vmaxv.s32 r0, q2
+# CHECK-NEXT: 1 2 2.00 vmaxv.u32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxav.s8 r0, q2
# CHECK-NEXT: 1 3 2.00 vmaxav.s16 r0, q2
-# CHECK-NEXT: 1 4 2.00 vmaxav.s32 r0, q2
+# CHECK-NEXT: 1 2 2.00 vmaxav.s32 r0, q2
# CHECK-NEXT: 1 1 2.00 vmin.s8 q0, q2, q1
# CHECK-NEXT: 1 1 2.00 vmin.u8 q0, q2, q1
# CHECK-NEXT: 1 1 2.00 vmin.s16 q0, q2, q1
@@ -649,15 +649,15 @@ vsub.i32 q0, q2, r0
# CHECK-NEXT: 1 1 2.00 vmina.s8 q0, q2
# CHECK-NEXT: 1 1 2.00 vmina.s16 q0, q2
# CHECK-NEXT: 1 1 2.00 vmina.s32 q0, q2
-# CHECK-NEXT: 1 2 2.00 vminv.s8 r0, q2
-# CHECK-NEXT: 1 2 2.00 vminv.u8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.u8 r0, q2
# CHECK-NEXT: 1 3 2.00 vminv.s16 r0, q2
# CHECK-NEXT: 1 3 2.00 vminv.u16 r0, q2
-# CHECK-NEXT: 1 4 2.00 vminv.s32 r0, q2
-# CHECK-NEXT: 1 4 2.00 vminv.u32 r0, q2
-# CHECK-NEXT: 1 2 2.00 vminav.s8 r0, q2
+# CHECK-NEXT: 1 2 2.00 vminv.s32 r0, q2
+# CHECK-NEXT: 1 2 2.00 vminv.u32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminav.s8 r0, q2
# CHECK-NEXT: 1 3 2.00 vminav.s16 r0, q2
-# CHECK-NEXT: 1 4 2.00 vminav.s32 r0, q2
+# CHECK-NEXT: 1 2 2.00 vminav.s32 r0, q2
# CHECK-NEXT: 1 2 2.00 vmla.i8 q0, q2, r0
# CHECK-NEXT: 1 2 2.00 vmla.i16 q0, q2, r0
# CHECK-NEXT: 1 2 2.00 vmla.i32 q0, q2, r0
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