[llvm] [RISCV] Match indices based on significant bits when forming strided ops (PR #65777)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 8 10:03:26 PDT 2023

Previous message: [llvm] [RISCV] Match indices based on significant bits when forming strided ops (PR #65777)
Next message: [llvm] [RISCV] Match indices based on significant bits when forming strided ops (PR #65777)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

topperc wrote:

Does this allow a vector of i8 indices like <0, 128, 0, 128, 0, 128, 0, 128> to be considered a stride of 128?

I'm traveling today so cant easily check.

https://github.com/llvm/llvm-project/pull/65777

Previous message: [llvm] [RISCV] Match indices based on significant bits when forming strided ops (PR #65777)
Next message: [llvm] [RISCV] Match indices based on significant bits when forming strided ops (PR #65777)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list