[llvm] d4d0b5e - Fix MIR failure after b922a362

[Qiu Chaofan via llvm-commits]

Author: Qiu Chaofan
Date: 2023-09-08T16:33:45+08:00
New Revision: d4d0b5eaab763abf04e99d96ff5bbc6e2d8fdb13

URL: https://github.com/llvm/llvm-project/commit/d4d0b5eaab763abf04e99d96ff5bbc6e2d8fdb13
DIFF: https://github.com/llvm/llvm-project/commit/d4d0b5eaab763abf04e99d96ff5bbc6e2d8fdb13.diff

LOG: Fix MIR failure after b922a362

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
    llvm/test/CodeGen/PowerPC/schedule-addi-load.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir b/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
index 058f6f0a2124b6..474c288bba88bf 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
@@ -18,11 +18,11 @@
   ; CHECK-LABEL: freeze_select
   ; CHECK:       # %bb.0:
   ; CHECK-NEXT:    xxlxor 0, 0, 0
-  ; CHECK-NEXT:    fcmpu 5, 2, 2
-  ; CHECK-NEXT:    fcmpu 1, 1, 1
-  ; CHECK-NEXT:    fcmpu 6, 2, 0
+  ; CHECK-NEXT:    fcmpu 1, 2, 2
+  ; CHECK-NEXT:    fcmpu 0, 2, 0
+  ; CHECK-NEXT:    crnor 20, 7, 2
   ; CHECK-NEXT:    fcmpu 0, 1, 0
-  ; CHECK-NEXT:    crnor 20, 23, 26
+  ; CHECK-NEXT:    fcmpu 1, 1, 1
   ; CHECK-NEXT:    crand 20, 2, 20
   ; CHECK-NEXT:    bclr 12, 20, 0
   ; CHECK-NEXT:  # %bb.1:

diff  --git a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir
index 9caa6765dfb4bd..1717238b2b7a0c 100644
--- a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir
+++ b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir
@@ -112,8 +112,8 @@ body:             |
     ; CHECK-P8: %5:g8rc_and_g8rc_nox0 = RLDICL %0, 0, 32
     ; CHECK-P8-NEXT: %6:gprc = LBZX %2, %5 :: (load (s8) from %ir.arrayidx)
     ; CHECK-P8-NEXT: %7:gprc = LBZX %3, %5 :: (load (s8) from %ir.arrayidx4)
-    ; CHECK-P8-NEXT: %8:crrc = CMPLW %6, %7
     ; CHECK-P8-NEXT: %9:g8rc = ADDI8 %5, 1
+    ; CHECK-P8-NEXT: %8:crrc = CMPLW %6, %7
     ; CHECK-P8-NEXT: BCC 76, %8
   
   bb.2.while.end: