[llvm] [AMDGPU] Add basic patterns to select lshl_or instead of v_perm (PR #65693)
Jeffrey Byrnes via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 7 16:07:01 PDT 2023
https://github.com/jrbyrnes created https://github.com/llvm/llvm-project/pull/65693:
It does the operation using fewer sreg.
Also, enables some future commits.
>From bbc097dd572e8783c6705696b2540c46ed6c48f5 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Thu, 7 Sep 2023 15:59:56 -0700
Subject: [PATCH] [AMDGPU] Add basic patterns to select lshl_or instead of
v_perm
Change-Id: I1c2d8c7ad10011189d66688385f2f40c022f4cf7
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 10 +++++++
.../test/CodeGen/AMDGPU/image-load-d16-tfe.ll | 8 +++---
.../CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 6 ++---
.../llvm.amdgcn.image.sample.d16.dim.ll | 16 +++++------
llvm/test/CodeGen/AMDGPU/load-hi16.ll | 27 +++++++------------
llvm/test/CodeGen/AMDGPU/pack.v2f16.ll | 6 ++---
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll | 6 ++---
llvm/test/CodeGen/AMDGPU/permute.ll | 27 +++++++++++++++++++
llvm/test/CodeGen/AMDGPU/trunc-combine.ll | 3 +--
9 files changed, 62 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index da6701fbcea1d21..d528dcaef9ae00b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2670,6 +2670,16 @@ def : GCNPat <
(V_PERM_B32_e64 (i32 0), VSrc_b32:$a, (S_MOV_B32 (i32 0x02030001)))
>;
+// We do not need an sreg to hold the immediate in LSHL_OR
+def : GCNPat <
+ (i32 (AMDGPUperm_impl i32:$a, i32:$b, (i32 0x01000504))),
+ (i32 (V_LSHL_OR_B32_e64 i32:$b, (i32 16), i32:$a))
+ >;
+
+def : GCNPat <
+ (i32 (AMDGPUperm_impl i32:$a, i32:$b, (i32 0x05040100))),
+ (i32 (V_LSHL_OR_B32_e64 i32:$a, (i32 16), i32:$b))
+ >;
}
def : GCNPat<
diff --git a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
index 83b650e2d755e23..9a2a84232adc662 100644
--- a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
@@ -544,9 +544,8 @@ define amdgpu_ps void @load_1d_v3f16_tfe_dmask7(<8 x i32> inreg %rsrc, i32 %s) {
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1
; GFX8-UNPACKED-NEXT: image_load v[1:4], v0, s[4:11] dmask:0x7 unorm tfe d16
-; GFX8-UNPACKED-NEXT: s_mov_b32 s0, 0x1000504
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
-; GFX8-UNPACKED-NEXT: v_perm_b32 v0, v1, v2, s0
+; GFX8-UNPACKED-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v3
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0
@@ -644,10 +643,9 @@ define amdgpu_ps void @load_1d_v4f16_tfe_dmask15(<8 x i32> inreg %rsrc, i32 %s)
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v5, v1
; GFX8-UNPACKED-NEXT: image_load v[1:5], v0, s[4:11] dmask:0xf unorm tfe d16
-; GFX8-UNPACKED-NEXT: s_mov_b32 s0, 0x1000504
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
-; GFX8-UNPACKED-NEXT: v_perm_b32 v3, v3, v4, s0
-; GFX8-UNPACKED-NEXT: v_perm_b32 v2, v1, v2, s0
+; GFX8-UNPACKED-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX8-UNPACKED-NEXT: v_lshl_or_b32 v2, v2, 16, v1
; GFX8-UNPACKED-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v5
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
index 4fa5b6cf843c1fa..95e16bade285edd 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -1692,7 +1692,6 @@ define amdgpu_kernel void @v_insertelement_v4f16_1(ptr addrspace(1) %out, ptr ad
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; VI-NEXT: v_mov_b32_e32 v4, 0x1000504
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
@@ -1702,7 +1701,7 @@ define amdgpu_kernel void @v_insertelement_v4f16_1(ptr addrspace(1) %out, ptr ad
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v0, v0, s4, v4
+; VI-NEXT: v_lshl_or_b32 v0, s4, 16, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
@@ -1849,7 +1848,6 @@ define amdgpu_kernel void @v_insertelement_v4f16_3(ptr addrspace(1) %out, ptr ad
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; VI-NEXT: v_mov_b32_e32 v4, 0x1000504
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
@@ -1859,7 +1857,7 @@ define amdgpu_kernel void @v_insertelement_v4f16_3(ptr addrspace(1) %out, ptr ad
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, s4, v4
+; VI-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index 7167dd93be80253..0efbad36121c90f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -232,9 +232,8 @@ define amdgpu_ps <2 x float> @image_sample_b_2d_v3f16(<8 x i32> inreg %rsrc, <4
; TONGA-NEXT: s_wqm_b64 exec, exec
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
; TONGA-NEXT: image_sample_b v[0:2], v[0:2], s[0:7], s[8:11] dmask:0x7 d16
-; TONGA-NEXT: s_mov_b32 s0, 0x1000504
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_perm_b32 v0, v0, v1, s0
+; TONGA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; TONGA-NEXT: v_mov_b32_e32 v1, v2
; TONGA-NEXT: ; return to shader part epilog
;
@@ -282,9 +281,8 @@ define amdgpu_ps <4 x float> @image_sample_b_2d_v3f16_tfe(<8 x i32> inreg %rsrc,
; TONGA-NEXT: v_mov_b32_e32 v6, v3
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
; TONGA-NEXT: image_sample_b v[3:6], v[0:2], s[0:7], s[8:11] dmask:0x7 tfe d16
-; TONGA-NEXT: s_mov_b32 s0, 0x1000504
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_perm_b32 v0, v3, v4, s0
+; TONGA-NEXT: v_lshl_or_b32 v0, v4, 16, v3
; TONGA-NEXT: v_mov_b32_e32 v1, v5
; TONGA-NEXT: v_mov_b32_e32 v2, v6
; TONGA-NEXT: ; return to shader part epilog
@@ -368,10 +366,9 @@ define amdgpu_ps <2 x float> @image_sample_b_2d_v4f16(<8 x i32> inreg %rsrc, <4
; TONGA-NEXT: s_wqm_b64 exec, exec
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
; TONGA-NEXT: image_sample_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf d16
-; TONGA-NEXT: s_mov_b32 s0, 0x1000504
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_perm_b32 v0, v0, v1, s0
-; TONGA-NEXT: v_perm_b32 v1, v2, v3, s0
+; TONGA-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; TONGA-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; TONGA-NEXT: ; return to shader part epilog
;
; GFX81-LABEL: image_sample_b_2d_v4f16:
@@ -418,10 +415,9 @@ define amdgpu_ps <4 x float> @image_sample_b_2d_v4f16_tfe(<8 x i32> inreg %rsrc,
; TONGA-NEXT: v_mov_b32_e32 v7, v3
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
; TONGA-NEXT: image_sample_b v[3:7], v[0:2], s[0:7], s[8:11] dmask:0xf tfe d16
-; TONGA-NEXT: s_mov_b32 s0, 0x1000504
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_perm_b32 v0, v3, v4, s0
-; TONGA-NEXT: v_perm_b32 v1, v5, v6, s0
+; TONGA-NEXT: v_lshl_or_b32 v0, v4, 16, v3
+; TONGA-NEXT: v_lshl_or_b32 v1, v6, 16, v5
; TONGA-NEXT: v_mov_b32_e32 v2, v7
; TONGA-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
index ba025a2202313fb..2da9c98989f1174 100644
--- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
@@ -266,9 +266,8 @@ define <2 x i16> @load_local_hi_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_hi_v2i16_reglo:
@@ -311,9 +310,8 @@ define void @load_local_hi_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -696,9 +694,8 @@ define void @load_global_hi_v2i16_reglo_vreg(ptr addrspace(1) %in, i16 %reg) #0
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX803-NEXT: flat_load_ushort v0, v[0:1]
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1006,9 +1003,8 @@ define void @load_flat_hi_v2i16_reglo_vreg(ptr %in, i16 %reg) #0 {
; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: flat_load_ushort v0, v[0:1]
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1300,9 +1296,8 @@ define void @load_private_hi_v2i16_reglo_vreg(ptr addrspace(5) byval(i16) %in, i
; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1399,8 +1394,7 @@ define void @load_private_hi_v2i16_reglo_vreg_nooff(ptr addrspace(5) byval(i16)
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
-; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1851,9 +1845,8 @@ define void @load_constant_hi_v2i16_reglo_vreg(ptr addrspace(4) %in, i16 %reg) #
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX803-NEXT: flat_load_ushort v0, v[0:1]
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -2069,9 +2062,8 @@ define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg, ptr addrspace(
; GFX803-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4058
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -2678,10 +2670,9 @@ define <2 x i16> @load_local_hi_v2i16_store_local_lo(i16 %reg, ptr addrspace(3)
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v2, v1
-; GFX803-NEXT: s_mov_b32 s4, 0x1000504
; GFX803-NEXT: ds_write_b16 v1, v0
; GFX803-NEXT: s_waitcnt lgkmcnt(1)
-; GFX803-NEXT: v_perm_b32 v2, v0, v2, s4
+; GFX803-NEXT: v_lshl_or_b32 v2, v2, 16, v0
; GFX803-NEXT: v_mov_b32_e32 v0, v2
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
index e21b93a386c3e78..be615399e095551 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
@@ -191,8 +191,7 @@ define amdgpu_kernel void @v_pack_v2f16(ptr addrspace(1) %in0, ptr addrspace(1)
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_mov_b32 s0, 0x1000504
-; GFX8-NEXT: v_perm_b32 v0, v0, v1, s0
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
@@ -271,10 +270,9 @@ define amdgpu_kernel void @v_pack_v2f16_user(ptr addrspace(1) %in0, ptr addrspac
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_mov_b32 s0, 0x1000504
; GFX8-NEXT: s_mov_b32 s3, 0x1100f000
; GFX8-NEXT: s_mov_b32 s2, -1
-; GFX8-NEXT: v_perm_b32 v0, v0, v1, s0
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 9, v0
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
index 4b21493bd7ca66d..538e6085428460d 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
@@ -187,8 +187,7 @@ define amdgpu_kernel void @v_pack_v2i16(ptr addrspace(1) %in0, ptr addrspace(1)
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_dword v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: s_mov_b32 s0, 0x1000504
-; GFX803-NEXT: v_perm_b32 v0, v0, v1, s0
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: ;;#ASMSTART
; GFX803-NEXT: ; use v0
; GFX803-NEXT: ;;#ASMEND
@@ -265,10 +264,9 @@ define amdgpu_kernel void @v_pack_v2i16_user(ptr addrspace(1) %in0, ptr addrspac
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_dword v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: s_mov_b32 s0, 0x1000504
; GFX803-NEXT: s_mov_b32 s3, 0x1100f000
; GFX803-NEXT: s_mov_b32 s2, -1
-; GFX803-NEXT: v_perm_b32 v0, v0, v1, s0
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 9, v0
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX803-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/permute.ll b/llvm/test/CodeGen/AMDGPU/permute.ll
index c6671fa51795439..a840defca1822ad 100644
--- a/llvm/test/CodeGen/AMDGPU/permute.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute.ll
@@ -392,4 +392,31 @@ bb:
ret void
}
+declare i32 @llvm.amdgcn.perm(i32, i32, i32) #0
+
+define amdgpu_ps void @v_perm_b32_lshl1(i32 %src1, i32 inreg %src2, ptr addrspace(1) %out) #1 {
+; GCN-LABEL: v_perm_b32_lshl1:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshl_or_b32 v0, s0, 16, v0
+; GCN-NEXT: flat_store_dword v[1:2], v0
+; GCN-NEXT: s_endpgm
+ %val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 16778500) #0
+ store i32 %val, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @v_perm_b32_lshl2(i32 %src1, i32 inreg %src2, ptr addrspace(1) %out) #1 {
+; GCN-LABEL: v_perm_b32_lshl2:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, s0
+; GCN-NEXT: flat_store_dword v[1:2], v0
+; GCN-NEXT: s_endpgm
+ %val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 84148480) #0
+ store i32 %val, ptr addrspace(1) %out
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x()
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
index d200b25c17d33bd..e7a3d12332a1da5 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
@@ -150,8 +150,7 @@ define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {
; VI-LABEL: trunc_v2i64_arg_to_v2i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x1000504
-; VI-NEXT: v_perm_b32 v0, v0, v2, s4
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc <2 x i64> %arg0 to <2 x i16>
ret <2 x i16> %trunc
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