[llvm] [RISCV] Add a combine to form masked.load from unit strided load (PR #65674)

[Craig Topper via llvm-commits]

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@@ -14076,6 +14053,25 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
       // By default we do not combine any intrinsic.
     default:
       return SDValue();
+    case Intrinsic::riscv_masked_strided_load: {
+      MVT VT = N->getSimpleValueType(0);
+      auto *Load = cast<MemIntrinsicSDNode>(N);
+      SDValue PassThru = N->getOperand(2);
+      SDValue Base = N->getOperand(3);
+      SDValue Stride = N->getOperand(4);
+      SDValue Mask = N->getOperand(5);
+
+      // If the stride is equal to the element size in bytes,  we can use
+      // a masked.load.
+      const unsigned ElementSizeInBits = VT.getScalarType().getSizeInBits();
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topperc wrote:

`getScalarStoreSize()`? Which will return the size in bytes.

https://github.com/llvm/llvm-project/pull/65674