[llvm] [RISCV] Lower constant build_vectors with few non-sign bits via vsext (PR #65648)

[Craig Topper via llvm-commits]

================
@@ -3456,6 +3456,27 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
   if (SDValue Res = lowerBuildVectorViaDominantValues(Op, DAG, Subtarget))
     return Res;
 
+  // IF the number of signbits allows, see if we can lower as a <N x i8>.
----------------
topperc wrote:

If the capitalization of 'F' in 'If' intentional?

https://github.com/llvm/llvm-project/pull/65648