[llvm] [AArch64][GlobalISel] Look through COPY and G_BITCAST while selecting fcvtl2 (fpext) (PR #65463)
Vladislav Dzhidzhoev via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 7 05:00:32 PDT 2023
https://github.com/dzhidzhoev updated https://github.com/llvm/llvm-project/pull/65463:
>From c0f6c10a0a01d0ed396ee4b0686227686bc1912f Mon Sep 17 00:00:00 2001
From: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: Fri, 1 Sep 2023 18:38:26 +0200
Subject: [PATCH 1/2] [AArch64][GlobalISel] Look through COPY and G_BITCAST
while selecting fcvtl2 (fpext)
It tackles some regressions introduced in
https://reviews.llvm.org/D144670.
---
.../GISel/AArch64InstructionSelector.cpp | 19 +++++++++++++----
llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll | 21 +++++++------------
2 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 57e6bb92057dc7d..5d75f30d7a00a39 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6777,10 +6777,21 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
MachineRegisterInfo &MRI =
Root.getParent()->getParent()->getParent()->getRegInfo();
- MachineInstr *Extract = getDefIgnoringCopies(Root.getReg(), MRI);
- if (Extract && Extract->getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
- Root.getReg() == Extract->getOperand(1).getReg()) {
- Register ExtReg = Extract->getOperand(2).getReg();
+ auto Extract = getDefSrcRegIgnoringCopies(Root.getReg(), MRI);
+ while (Extract && Extract->MI->getOpcode() == TargetOpcode::G_BITCAST)
+ Extract =
+ getDefSrcRegIgnoringCopies(Extract->MI->getOperand(1).getReg(), MRI);
+ if (!Extract)
+ return std::nullopt;
+
+ if (Extract->MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) {
+ if (Extract->Reg == Extract->MI->getOperand(1).getReg()) {
+ Register ExtReg = Extract->MI->getOperand(2).getReg();
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
+ }
+ }
+ if (Extract->MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT) {
+ Register ExtReg = Extract->MI->getOperand(1).getReg();
return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll b/llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
index eacb7731eced4e4..269ffed98a844eb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
@@ -46,8 +46,7 @@ define <2 x double> @test_vcvt_high_v1f64_f32_bitcast(<4 x float> %x) nounwind r
;
; GISEL-LABEL: test_vcvt_high_v1f64_f32_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.2d, v0.2s
+; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
; GISEL-NEXT: ret
%bc1 = bitcast <4 x float> %x to <2 x double>
%ext = shufflevector <2 x double> %bc1, <2 x double> undef, <1 x i32> <i32 1>
@@ -64,8 +63,7 @@ define <2 x double> @test_vcvt_high_v1i64_f32_bitcast(<2 x i64> %x) nounwind rea
;
; GISEL-LABEL: test_vcvt_high_v1i64_f32_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.2d, v0.2s
+; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
; GISEL-NEXT: ret
%ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>
%bc2 = bitcast <1 x i64> %ext to <2 x float>
@@ -97,8 +95,7 @@ define <2 x double> @test_vcvt_high_v4i16_f32_bitcast(<8 x i16> %x) nounwind rea
;
; GISEL-LABEL: test_vcvt_high_v4i16_f32_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.2d, v0.2s
+; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
; GISEL-NEXT: ret
%ext = shufflevector <8 x i16> %x, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%bc2 = bitcast <4 x i16> %ext to <2 x float>
@@ -114,8 +111,7 @@ define <2 x double> @test_vcvt_high_v8i8_f32_bitcast(<16 x i8> %x) nounwind read
;
; GISEL-LABEL: test_vcvt_high_v8i8_f32_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.2d, v0.2s
+; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
; GISEL-NEXT: ret
%ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%bc2 = bitcast <8 x i8> %ext to <2 x float>
@@ -131,8 +127,7 @@ define <4 x float> @test_vcvt_high_v1i64_f16_bitcast(<2 x i64> %x) nounwind read
;
; GISEL-LABEL: test_vcvt_high_v1i64_f16_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.4s, v0.4h
+; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
; GISEL-NEXT: ret
%ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>
%bc2 = bitcast <1 x i64> %ext to <4 x half>
@@ -148,8 +143,7 @@ define <4 x float> @test_vcvt_high_v2i32_f16_bitcast(<4 x i32> %x) nounwind read
;
; GISEL-LABEL: test_vcvt_high_v2i32_f16_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.4s, v0.4h
+; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
; GISEL-NEXT: ret
%ext = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%bc2 = bitcast <2 x i32> %ext to <4 x half>
@@ -181,8 +175,7 @@ define <4 x float> @test_vcvt_high_v8i8_f16_bitcast(<16 x i8> %x) nounwind readn
;
; GISEL-LABEL: test_vcvt_high_v8i8_f16_bitcast:
; GISEL: // %bb.0:
-; GISEL-NEXT: mov d0, v0[1]
-; GISEL-NEXT: fcvtl v0.4s, v0.4h
+; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
; GISEL-NEXT: ret
%ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%bc2 = bitcast <8 x i8> %ext to <4 x half>
>From 0245f5418a423a9fe728b333f037d6a8513a0b11 Mon Sep 17 00:00:00 2001
From: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: Thu, 7 Sep 2023 13:59:24 +0200
Subject: [PATCH 2/2] Addressed @davemgreen comments.
---
.../AArch64/GISel/AArch64InstructionSelector.cpp | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 5d75f30d7a00a39..b64dd9160bfb01e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6778,7 +6778,8 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
Root.getParent()->getParent()->getParent()->getRegInfo();
auto Extract = getDefSrcRegIgnoringCopies(Root.getReg(), MRI);
- while (Extract && Extract->MI->getOpcode() == TargetOpcode::G_BITCAST)
+ while (Extract && Extract->MI->getOpcode() == TargetOpcode::G_BITCAST &&
+ STI.isLittleEndian())
Extract =
getDefSrcRegIgnoringCopies(Extract->MI->getOperand(1).getReg(), MRI);
if (!Extract)
@@ -6791,8 +6792,15 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
}
}
if (Extract->MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT) {
- Register ExtReg = Extract->MI->getOperand(1).getReg();
- return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
+ LLT SrcTy = MRI.getType(Extract->MI->getOperand(1).getReg());
+ auto LaneIdx = getIConstantVRegValWithLookThrough(
+ Extract->MI->getOperand(2).getReg(), MRI);
+ if (LaneIdx &&
+ SrcTy == LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)) &&
+ LaneIdx->Value.getSExtValue() == 1) {
+ Register ExtReg = Extract->MI->getOperand(1).getReg();
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
+ }
}
return std::nullopt;
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