[PATCH] D157540: [JITLink][AArch32] Fixes for initial AArc32 backend

[Stefan Gränitz via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3e7cd5ea1e9b: [JITLink][AArch32] Fixes for initial AArch32 backend (authored by Eymay, committed by sgraenitz).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157540/new/

https://reviews.llvm.org/D157540

Files:
  llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
  llvm/lib/ExecutionEngine/JITLink/aarch32.cpp


Index: llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
===================================================================
--- llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
+++ llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
@@ -175,7 +175,7 @@
 template <EdgeKind_aarch32 Kind>
 void writeRegister(WritableThumbRelocation &R, HalfWords Reg) {
   static constexpr HalfWords Mask = FixupInfo<Kind>::RegMask;
-  assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Hi & Reg.Hi) == Reg.Hi &&
+  assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Lo & Reg.Lo) == Reg.Lo &&
          "Value bits exceed bit range of given mask");
   R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi;
   R.Lo = (R.Lo & ~Mask.Lo) | Reg.Lo;
@@ -184,7 +184,7 @@
 template <EdgeKind_aarch32 Kind>
 void writeImmediate(WritableThumbRelocation &R, HalfWords Imm) {
   static constexpr HalfWords Mask = FixupInfo<Kind>::ImmMask;
-  assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Hi & Imm.Hi) == Imm.Hi &&
+  assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Lo & Imm.Lo) == Imm.Lo &&
          "Value bits exceed bit range of given mask");
   R.Hi = (R.Hi & ~Mask.Hi) | Imm.Hi;
   R.Lo = (R.Lo & ~Mask.Lo) | Imm.Lo;
@@ -242,10 +242,6 @@
   case Thumb_Jump24:
     if (!checkOpcode<Thumb_Jump24>(R))
       return makeUnexpectedOpcodeError(G, R, Kind);
-    if (R.Lo & FixupInfo<Thumb_Jump24>::LoBitConditional)
-      return make_error<JITLinkError>("Relocation expects an unconditional "
-                                      "B.W branch instruction: " +
-                                      StringRef(G.getEdgeKindName(Kind)));
     return LLVM_LIKELY(ArmCfg.J1J2BranchEncoding)
                   ? decodeImmBT4BlT1BlxT2_J1J2(R.Hi, R.Lo)
                   : decodeImmBT4BlT1BlxT2(R.Hi, R.Lo);
@@ -352,10 +348,6 @@
   case Thumb_Jump24: {
     if (!checkOpcode<Thumb_Jump24>(R))
       return makeUnexpectedOpcodeError(G, R, Kind);
-    if (R.Lo & FixupInfo<Thumb_Jump24>::LoBitConditional)
-      return make_error<JITLinkError>("Relocation expects an unconditional "
-                                      "B.W branch instruction: " +
-                                      StringRef(G.getEdgeKindName(Kind)));
     if (!(TargetSymbol.hasTargetFlags(ThumbSymbol)))
       return make_error<JITLinkError>("Branch relocation needs interworking "
                                       "stub when bridging to ARM: " +
@@ -471,6 +463,7 @@
 
   switch (K) {
     KIND_NAME_CASE(Data_Delta32)
+    KIND_NAME_CASE(Data_Pointer32)
     KIND_NAME_CASE(Arm_Call)
     KIND_NAME_CASE(Thumb_Call)
     KIND_NAME_CASE(Thumb_Jump24)
Index: llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
===================================================================
--- llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
+++ llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
@@ -149,7 +149,6 @@
   static constexpr HalfWords Opcode{0xf000, 0x8000};
   static constexpr HalfWords OpcodeMask{0xf800, 0x8000};
   static constexpr HalfWords ImmMask{0x07ff, 0x2fff};
-  static constexpr uint16_t LoBitConditional = 0x1000;
 };
 
 template <> struct FixupInfo<Thumb_Call> {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D157540.556002.patch
Type: text/x-patch
Size: 3086 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230906/e4e47f6b/attachment.bin>