[PATCH] D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 6 01:19:45 PDT 2023
wangpc updated this revision to Diff 555981.
wangpc marked an inline comment as done.
wangpc edited the summary of this revision.
wangpc added a comment.
Rename `sew_div_8` to `sewDividedBy8`.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159368/new/
https://reviews.llvm.org/D159368
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/copyprop.mir
llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D159368.555981.patch
Type: text/x-patch
Size: 197948 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230906/fe6effd6/attachment-0001.bin>
More information about the llvm-commits
mailing list