[llvm] e086e0a - [X86] Add test coverage for new smulo folds added in D159406

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-09-05T17:43:42+01:00
New Revision: e086e0aeef6be3b1b3b403e54fbe2669c649973d

URL: https://github.com/llvm/llvm-project/commit/e086e0aeef6be3b1b3b403e54fbe2669c649973d
DIFF: https://github.com/llvm/llvm-project/commit/e086e0aeef6be3b1b3b403e54fbe2669c649973d.diff

LOG: [X86] Add test coverage for new smulo folds added in D159406

Pulled from the InstCombine with_overflow.ll tests

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-mulo.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/combine-mulo.ll b/llvm/test/CodeGen/X86/combine-mulo.ll
index 683c78623c22952..e97cb589ab117e5 100644
--- a/llvm/test/CodeGen/X86/combine-mulo.ll
+++ b/llvm/test/CodeGen/X86/combine-mulo.ll
@@ -88,3 +88,62 @@ define <4 x i32> @combine_vec_umul_two(<4 x i32> %a0, <4 x i32> %a1) {
   %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
   ret <4 x i32> %4
 }
+
+define { i32, i1 } @combine_smul_nsw(i32 %a, i32 %b) {
+; CHECK-LABEL: combine_smul_nsw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    andl $4095, %edi # imm = 0xFFF
+; CHECK-NEXT:    andl $524287, %eax # imm = 0x7FFFF
+; CHECK-NEXT:    imull %edi, %eax
+; CHECK-NEXT:    seto %dl
+; CHECK-NEXT:    retq
+  %aa = and i32 %a, 4095 ; 0xfff
+  %bb = and i32 %b, 524287; 0x7ffff
+  %x = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %aa, i32 %bb)
+  ret { i32, i1 } %x
+}
+
+define { <4 x i32>, <4 x i1> } @combine_vec_smul_nsw(<4 x i32> %a, <4 x i32> %b) {
+; SSE-LABEL: combine_vec_smul_nsw:
+; SSE:       # %bb.0:
+; SSE-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE-NEXT:    pmuldq %xmm2, %xmm3
+; SSE-NEXT:    movdqa %xmm0, %xmm2
+; SSE-NEXT:    pmuldq %xmm1, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
+; SSE-NEXT:    pxor %xmm3, %xmm3
+; SSE-NEXT:    pcmpeqd %xmm2, %xmm3
+; SSE-NEXT:    pcmpeqd %xmm2, %xmm2
+; SSE-NEXT:    pxor %xmm3, %xmm2
+; SSE-NEXT:    pmulld %xmm1, %xmm0
+; SSE-NEXT:    movdqa %xmm2, %xmm1
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_smul_nsw:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [4095,4095,4095,4095]
+; AVX-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [524287,524287,524287,524287]
+; AVX-NEXT:    vpand %xmm2, %xmm1, %xmm2
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; AVX-NEXT:    vpmuldq %xmm1, %xmm3, %xmm1
+; AVX-NEXT:    vpmuldq %xmm2, %xmm0, %xmm3
+; AVX-NEXT:    vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT:    vpblendd {{.*#+}} xmm1 = xmm3[0],xmm1[1],xmm3[2],xmm1[3]
+; AVX-NEXT:    vpxor %xmm3, %xmm3, %xmm3
+; AVX-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
+; AVX-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX-NEXT:    vpxor %xmm3, %xmm1, %xmm1
+; AVX-NEXT:    vpmulld %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %aa = and <4 x i32> %a, <i32 4095, i32 4095, i32 4095, i32 4095>
+  %bb = and <4 x i32> %b, <i32 524287, i32 524287, i32 524287, i32 524287>
+  %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %aa, <4 x i32> %bb)
+  ret { <4 x i32>, <4 x i1> } %x
+}