[llvm] bb1a03d - Addressed @aemerson comments

[Vladislav Dzhidzhoev via llvm-commits]

Author: Vladislav Dzhidzhoev
Date: 2023-09-05T16:00:49+02:00
New Revision: bb1a03df47b2efe6c60fd7fa510b9e77109a9236

URL: https://github.com/llvm/llvm-project/commit/bb1a03df47b2efe6c60fd7fa510b9e77109a9236
DIFF: https://github.com/llvm/llvm-project/commit/bb1a03df47b2efe6c60fd7fa510b9e77109a9236.diff

LOG: Addressed @aemerson comments

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index d2a99b65cc6aab..9640a1c17b87c3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -1070,14 +1070,13 @@ void applyVectorSextInReg(MachineInstr &MI, MachineRegisterInfo &MRI,
 ///           => unused, <N x t> = unmerge v
 bool matchUnmergeExtToUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
                               Register &MatchInfo) {
-  assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
   auto &Unmerge = cast<GUnmerge>(MI);
   if (Unmerge.getNumDefs() != 2)
     return false;
-  if (!MRI.use_nodbg_empty(Unmerge.getOperand(1).getReg()))
+  if (!MRI.use_nodbg_empty(Unmerge.getReg(1)))
     return false;
 
-  LLT DstTy = MRI.getType(Unmerge.getOperand(0).getReg());
+  LLT DstTy = MRI.getType(Unmerge.getReg(0));
   if (!DstTy.isVector())
     return false;