[PATCH] D159443: [AArch64] Fix schedmodel zero latency moves for Neoverse V2

[Ricardo Jesus via Phabricator via llvm-commits]

rjj marked an inline comment as done.
rjj added a comment.

In D159443#4638215 <https://reviews.llvm.org/D159443#4638215>, @SjoerdMeijer wrote:

> I agree with these observations, wrote a couple of micro-benchmarks, and think that on Grace I can confirm:
>
>> These instructions do not utilize the scheduling and execution resources of the machine.
>
> (taken from the SWOG).
>
> I am assuming that fixing this helps LLVM-MCA? I don't expect this to make a difference for performance of the codegen, but what I can offer is to check that with a couple of performance runs on hardware as I am assuming you haven't been able to verify that.
>
> I added one question inline, and am also curious what Dave thinks about this.

Yep, the main aim of this is to make MCA a bit more accurate. If you could check performance on hardware that would be great!

Cheers,
Ricardo



================
Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s:2535
 # CHECK-NEXT:  1      2     0.50                        tst	x2, x20, asr #2
-# CHECK-NEXT:  1      1     0.17                        mov	x3, x6
-# CHECK-NEXT:  1      1     0.17                        mov	x3, xzr
-# CHECK-NEXT:  1      1     0.17                        mov	wzr, w2
-# CHECK-NEXT:  1      1     0.17                        mov	w3, w5
+# CHECK-NEXT:  1      0     0.06                        mov	x3, x6
+# CHECK-NEXT:  1      0     0.06                        mov	x3, xzr
----------------
SjoerdMeijer wrote:
> This MOV seems to be affected, but doesn't seem to right?
That should be the last MOV listed on §4.12, `MOV Xd, Xn`.


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