[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

Tue Sep 5 06:03:05 PDT 2023

asb added a comment.

Left a trivial comment. Not sure on this vs D158396 <https://reviews.llvm.org/D158396> - the logic of the other patch does seem a bit easier to follow as you suggested in your comment there.

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Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:34

 // Same as CSR_Interrupt, but including all 32-bit FP registers.
 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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We should probably mention fcsr in this comment (and the one for f64 below).

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https://reviews.llvm.org/D158492