[llvm] [AArch64][SME] Various tests should work with +sme, just as they do for +sve (PR #65260)

[Matthew Devereau via llvm-commits]

================
@@ -3961,7 +3961,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRHui;
     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
-      assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+      assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE");
----------------
MDevereau wrote:

```suggestion
      assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE or SME");
```
This should be updated to reflect the actual assertion behaviour.

https://github.com/llvm/llvm-project/pull/65260