[llvm] 2f3a362 - [SPARC][IAS] Add v9 encoding of %fq

[Brad Smith via llvm-commits]

Author: Koakuma
Date: 2023-09-05T04:37:18-04:00
New Revision: 2f3a362cc06eb3f08bedd24d963cd892a01f9e72

URL: https://github.com/llvm/llvm-project/commit/2f3a362cc06eb3f08bedd24d963cd892a01f9e72
DIFF: https://github.com/llvm/llvm-project/commit/2f3a362cc06eb3f08bedd24d963cd892a01f9e72.diff

LOG: [SPARC][IAS] Add v9 encoding of %fq

While both SPARCv7/v8 and v9 has a register named %fq, they encode it
differently, so we need to differentiate between them.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D157232

Added: 
    

Modified: 
    llvm/lib/Target/Sparc/SparcInstrInfo.td
    llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
    llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
    llvm/test/MC/Sparc/sparcv9-instructions.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 61723550969138f..c85c891d41a9047 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1769,6 +1769,15 @@ let rs2 = 0 in
   def RDPR : F3_1<2, 0b101010,
                  (outs IntRegs:$rd), (ins PRRegs:$rs1),
                  "rdpr $rs1, $rd", []>;
+
+// Special case %fq as the register is also used in V8
+// (albeit with 
diff erent instructions and encoding).
+// This allows us to reuse the register definition and
+// the "%fq" designation while giving it a 
diff erent encoding.
+let Uses = [FQ], rs1 = 15, rs2 = 0 in
+  def RDFQ : F3_1<2, 0b101010,
+                 (outs IntRegs:$rd), (ins),
+                 "rdpr %fq, $rd", []>;
 }
 
 // Section A.62 - Write Privileged Register Instructions

diff  --git a/llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt b/llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
index a5d146b03e6486c..56ffb9abd5341ae 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
@@ -37,7 +37,9 @@
 # CHECK: st %fsr, [%i5]
 0xc1 0x2f 0x40 0x00
 
-# CHECK: std %fq, [%i5+%l1]
+## The same encoding resolves to 
diff erent instructions in V8 and V9.
+# V8: std %fq, [%i5+%l1]
+# V9: stq %f0, [%i5+%l1]
 0xc1 0x37 0x40 0x11
 
 

diff  --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
index 612003a24df0287..da278e1832767d8 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
@@ -149,3 +149,6 @@
 
 # CHECK: restored
 0x83,0x88,0x00,0x00
+
+# CHECK: rdpr %fq, %i5
+0xbb,0x53,0xc0,0x00

diff  --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index 23e9f0798576f43..2a90d4dc0387d42 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -416,6 +416,10 @@
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
 
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rdpr %fq,%i5
+        ! V9: rdpr %fq, %i5             ! encoding: [0xbb,0x53,0xc0,0x00]
+        rdpr %fq,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %ver,%i5
         ! V9: rdpr %ver, %i5            ! encoding: [0xbb,0x57,0xc0,0x00]