[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store

Ting Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 5 00:31:00 PDT 2023


tingwang added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:17105
+        // be generated.
+        if (TailSize > 2 && TailSize <= 4) {
+          return MVT::v8i16;
----------------
shchenz wrote:
> If using `stfd` is allowed for tail size 5/6/7, then can we use `stfd` for tail size 3/4 too? (I assume the change here impacts cases `memsetTailV1B3` and `memsetTailV1B4`?)
It seems `TargetLowering::findOptimalMemOpLowering()` decides the type of each store. I guess if we change the type for the size 3/4 case from i32 to i64, then it will result in stfd.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138883/new/

https://reviews.llvm.org/D138883



More information about the llvm-commits mailing list