[llvm] [PowerPC] Prefer xxsel for vector selection (PR #65295)
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 4 23:06:29 PDT 2023
https://github.com/ecnelises created https://github.com/llvm/llvm-project/pull/65295:
None
>From 092881cd59c21b1608d47037695ea5132a77e24f Mon Sep 17 00:00:00 2001
From: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: Tue, 5 Sep 2023 14:01:02 +0800
Subject: [PATCH] [PowerPC] Prefer xxsel for vector selection
---
llvm/lib/Target/PowerPC/PPCInstrVSX.td | 38 +++++++++++++++++++
llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll | 20 +++++-----
llvm/test/CodeGen/PowerPC/vec_select.ll | 4 +-
.../test/CodeGen/PowerPC/vselect-constants.ll | 10 ++---
llvm/test/CodeGen/PowerPC/vsx.ll | 16 ++++----
5 files changed, 62 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 0e5f6b773bb544..3a2add6c8900a1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2707,6 +2707,44 @@ def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
(XXSEL $vC, $vB, $vA)>;
def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
(XXSEL $vC, $vB, $vA)>;
+
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETEQ)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPEQDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETNE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPEQDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETGE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPGEDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETLT)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPGEDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETGT)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPGTDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETLE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPGTDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOEQ)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPEQDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETONE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPEQDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOGE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPGEDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOLT)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPGEDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOGT)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $fval, $tval, (XVCMPGTDP $lhs, $rhs))>;
+def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOLE)),
+ v4i32:$tval, v4i32:$fval),
+ (XXSEL $tval, $fval, (XVCMPGTDP $lhs, $rhs))>;
+
def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)),
(COPY_TO_REGCLASS
(XXSEL (COPY_TO_REGCLASS $vC, VSRC),
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
index 342a9044b9bcc5..5f06ffabc28217 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
@@ -1843,10 +1843,10 @@ define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {
;
; CHECK-PWR78-LABEL: absd_int32_sgt:
; CHECK-PWR78: # %bb.0:
-; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
-; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
+; CHECK-PWR78-NEXT: xvcmpgtdp vs0, v2, v3
+; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
-; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
+; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
; CHECK-PWR78-NEXT: blr
%3 = icmp sgt <4 x i32> %0, %1
%4 = sub <4 x i32> %0, %1
@@ -1865,8 +1865,7 @@ define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {
;
; CHECK-PWR78-LABEL: absd_int32_sge:
; CHECK-PWR78: # %bb.0:
-; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
-; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
+; CHECK-PWR78-NEXT: xvcmpgedp vs0, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
@@ -1888,10 +1887,10 @@ define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {
;
; CHECK-PWR78-LABEL: absd_int32_slt:
; CHECK-PWR78: # %bb.0:
-; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
-; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
+; CHECK-PWR78-NEXT: xvcmpgedp vs0, v2, v3
+; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
-; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
+; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
; CHECK-PWR78-NEXT: blr
%3 = icmp slt <4 x i32> %0, %1
%4 = sub <4 x i32> %0, %1
@@ -1910,11 +1909,10 @@ define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {
;
; CHECK-PWR78-LABEL: absd_int32_sle:
; CHECK-PWR78: # %bb.0:
-; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
-; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
+; CHECK-PWR78-NEXT: xvcmpgtdp vs0, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
-; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
+; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
; CHECK-PWR78-NEXT: blr
%3 = icmp sle <4 x i32> %0, %1
%4 = sub <4 x i32> %0, %1
diff --git a/llvm/test/CodeGen/PowerPC/vec_select.ll b/llvm/test/CodeGen/PowerPC/vec_select.ll
index 2a839675b2a87a..f7ff88a1437dfe 100644
--- a/llvm/test/CodeGen/PowerPC/vec_select.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_select.ll
@@ -86,8 +86,8 @@ entry:
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
; CHECK-VSX-LABEL: test5:
; CHECK-VSX: # %bb.0: # %entry
-; CHECK-VSX-NEXT: vcmpequw v4, v4, v5
-; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4
+; CHECK-VSX-NEXT: xvcmpeqdp vs0, v4, v5
+; CHECK-VSX-NEXT: xxsel v2, v3, v2, vs0
; CHECK-VSX-NEXT: blr
;
; CHECK-NOVSX-LABEL: test5:
diff --git a/llvm/test/CodeGen/PowerPC/vselect-constants.ll b/llvm/test/CodeGen/PowerPC/vselect-constants.ll
index d2d331b0a078c5..84a6c07c39c2e5 100644
--- a/llvm/test/CodeGen/PowerPC/vselect-constants.ll
+++ b/llvm/test/CodeGen/PowerPC/vselect-constants.ll
@@ -34,14 +34,14 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI1_1 at toc@ha
-; CHECK-NEXT: vcmpequw 2, 2, 3
+; CHECK-NEXT: xvcmpeqdp 1, 34, 35
; CHECK-NEXT: addi 3, 3, .LCPI1_0 at toc@l
; CHECK-NEXT: addi 4, 4, .LCPI1_1 at toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
-; CHECK-NEXT: lxvd2x 1, 0, 4
-; CHECK-NEXT: xxswapd 35, 0
-; CHECK-NEXT: xxswapd 36, 1
-; CHECK-NEXT: xxsel 34, 36, 35, 34
+; CHECK-NEXT: lxvd2x 2, 0, 4
+; CHECK-NEXT: xxswapd 34, 0
+; CHECK-NEXT: xxswapd 35, 2
+; CHECK-NEXT: xxsel 34, 35, 34, 1
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll
index e42e2ae2433262..5d442510e945ca 100644
--- a/llvm/test/CodeGen/PowerPC/vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx.ll
@@ -558,26 +558,26 @@ entry:
define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
; CHECK-LABEL: test20:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcmpequw v4, v4, v5
-; CHECK-NEXT: xxsel v2, v3, v2, v4
+; CHECK-NEXT: xvcmpeqdp vs0, v4, v5
+; CHECK-NEXT: xxsel v2, v3, v2, vs0
; CHECK-NEXT: blr
;
; CHECK-REG-LABEL: test20:
; CHECK-REG: # %bb.0: # %entry
-; CHECK-REG-NEXT: vcmpequw v4, v4, v5
-; CHECK-REG-NEXT: xxsel v2, v3, v2, v4
+; CHECK-REG-NEXT: xvcmpeqdp vs0, v4, v5
+; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0
; CHECK-REG-NEXT: blr
;
; CHECK-FISL-LABEL: test20:
; CHECK-FISL: # %bb.0: # %entry
-; CHECK-FISL-NEXT: vcmpequw v4, v4, v5
-; CHECK-FISL-NEXT: xxsel v2, v3, v2, v4
+; CHECK-FISL-NEXT: xvcmpeqdp vs0, v4, v5
+; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
; CHECK-FISL-NEXT: blr
;
; CHECK-LE-LABEL: test20:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: vcmpequw v4, v4, v5
-; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
+; CHECK-LE-NEXT: xvcmpeqdp vs0, v4, v5
+; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0
; CHECK-LE-NEXT: blr
entry:
%m = icmp eq <4 x i32> %c, %d
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