[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:17105
+        // be generated.
+        if (TailSize > 2 && TailSize <= 4) {
+          return MVT::v8i16;
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If using `stfd` is allowed for tail size 5/6/7, then can we use `stfd` for tail size 3/4 too? (I assume the change here impacts cases `memsetTailV1B3` and `memsetTailV1B4`?)


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Comment at: llvm/test/CodeGen/PowerPC/memset-tail.ll:244
+; P8-LE-NEXT:    li 4, 15
+; P8-LE-NEXT:    stxsdx 34, 3, 4
 ; P8-LE-NEXT:    stxvd2x 34, 0, 3
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This seems a legacy issue because I also found same issue in case `memsetTailV1B12` and also from the left side of this case.

Is it safe to extend the store length from 23 bytes to 32(or 24) bytes here? There is no clue saying that memory after `(char *)p + 7` is writable by the user?

The related logic is in `allowsMisalignedMemoryAccesses()`. But is it correct that we can safely assume this memset can write more memory even this memset handles aligned memory?

What do you think? @nemanjai 


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  https://reviews.llvm.org/D138883/new/

https://reviews.llvm.org/D138883