[llvm] f5fb6ad - AMDGPU: Precommit a test file

[Nicolai Hähnle via llvm-commits]

Author: Nicolai Hähnle
Date: 2023-09-05T00:17:46+02:00
New Revision: f5fb6ad2e5a79b9abbb363b9a7cb9b746b623be3

URL: https://github.com/llvm/llvm-project/commit/f5fb6ad2e5a79b9abbb363b9a7cb9b746b623be3
DIFF: https://github.com/llvm/llvm-project/commit/f5fb6ad2e5a79b9abbb363b9a7cb9b746b623be3.diff

LOG: AMDGPU: Precommit a test file

Demonstrates bad scheduling for private load/store vs. buffer
intrinsics.

Added: 
    llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll b/llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
new file mode 100644
index 00000000000000..4f21106b0999ca
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -o - < %s | FileCheck --prefixes=CHECK %s
+
+define amdgpu_gfx void @example(<4 x i32> inreg %rsrc, ptr addrspace(5) %src, i32 %dst) {
+; CHECK-LABEL: example:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    scratch_load_b32 v2, v0, off
+; CHECK-NEXT:    v_add_nc_u32_e32 v0, 4, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    buffer_store_b32 v2, v1, s[4:7], 0 offen
+; CHECK-NEXT:    scratch_load_b32 v0, v0, off
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    buffer_store_b32 v0, v1, s[4:7], 0 offen offset:4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+;
+  %x0 = load i32, ptr addrspace(5) %src
+  call void @llvm.amdgcn.raw.buffer.store.i32(i32 %x0, <4 x i32> %rsrc, i32 %dst, i32 0, i32 0)
+  %src1 = getelementptr i8, ptr addrspace(5) %src, i32 4
+  %x1 = load i32, ptr addrspace(5) %src1
+  %dst1 = add i32 %dst, 4
+  call void @llvm.amdgcn.raw.buffer.store.i32(i32 %x1, <4 x i32> %rsrc, i32 %dst1, i32 0, i32 0)
+  ret void
+}
+
+declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32)