[llvm] e6971cb - [X86] combine-mulo.ll - add common CHECK prefix for SSE/AVX test runs

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-09-04T16:42:48+01:00
New Revision: e6971cbc06d131bbb24488ecd52a664b63005be7

URL: https://github.com/llvm/llvm-project/commit/e6971cbc06d131bbb24488ecd52a664b63005be7
DIFF: https://github.com/llvm/llvm-project/commit/e6971cbc06d131bbb24488ecd52a664b63005be7.diff

LOG: [X86] combine-mulo.ll - add common CHECK prefix for SSE/AVX test runs

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-mulo.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-mulo.ll b/llvm/test/CodeGen/X86/combine-mulo.ll
index 9dffc70f6831457..683c78623c22952 100644
--- a/llvm/test/CodeGen/X86/combine-mulo.ll
+++ b/llvm/test/CodeGen/X86/combine-mulo.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
 
 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
@@ -10,19 +10,12 @@ declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32
 
 ; fold (smulo x, 2) -> (saddo x, x)
 define i32 @combine_smul_two(i32 %a0, i32 %a1) {
-; SSE-LABEL: combine_smul_two:
-; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
-; SSE-NEXT:    addl %edi, %eax
-; SSE-NEXT:    cmovol %esi, %eax
-; SSE-NEXT:    retq
-;
-; AVX-LABEL: combine_smul_two:
-; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
-; AVX-NEXT:    addl %edi, %eax
-; AVX-NEXT:    cmovol %esi, %eax
-; AVX-NEXT:    retq
+; CHECK-LABEL: combine_smul_two:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    cmovol %esi, %eax
+; CHECK-NEXT:    retq
   %1 = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a0, i32 2)
   %2 = extractvalue {i32, i1} %1, 0
   %3 = extractvalue {i32, i1} %1, 1
@@ -58,19 +51,12 @@ define <4 x i32> @combine_vec_smul_two(<4 x i32> %a0, <4 x i32> %a1) {
 
 ; fold (umulo x, 2) -> (uaddo x, x)
 define i32 @combine_umul_two(i32 %a0, i32 %a1) {
-; SSE-LABEL: combine_umul_two:
-; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
-; SSE-NEXT:    addl %edi, %eax
-; SSE-NEXT:    cmovbl %esi, %eax
-; SSE-NEXT:    retq
-;
-; AVX-LABEL: combine_umul_two:
-; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
-; AVX-NEXT:    addl %edi, %eax
-; AVX-NEXT:    cmovbl %esi, %eax
-; AVX-NEXT:    retq
+; CHECK-LABEL: combine_umul_two:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    cmovbl %esi, %eax
+; CHECK-NEXT:    retq
   %1 = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %a0, i32 2)
   %2 = extractvalue {i32, i1} %1, 0
   %3 = extractvalue {i32, i1} %1, 1