[PATCH] D154488: [PowerPC] Define SchedModel for Power8

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:210
+    (instregex "^(ADD|SUBF)(M|Z)?E(8)?_rec$"),
+    (instregex "^(ADD|SUBF|NEG)(4|8)?_rec$"),
+    NOP, ADDG6S, ADDG6S8, ADDZE, ADDZE8, ADDIC_rec, NEGO_rec, ADDC, ADDC8, SUBFC, SUBFC8,
----------------
qiucf wrote:
> shchenz wrote:
> > hmm, this change seems still not accurate, below is from PWR8 UM(17 March 2016)
> > ```
> > addi addis add add. subf subf. addic subfic adde addme subfme subfze neg neg. nego
> > FXU (or LU or LSU for non-dot forms)
> > ```
> > 
> > `add.` should be able to use FXU or LU (4 hardware units).
> > 
> > Maybe we need to define a new unit group like `P8_FX_LU` for this kind of instructions?
> > 
> > I suggest you check other instructions as well compared with the UM.
> > 
> > Thanks very much for the big effort.
> Per my understanding, only non-dot forms use LU/LSU?
OK, so we have different understanding about `FXU (or LU or LSU for non-dot forms)`.

Let us use yours for now until we find a clear doc about what units dot form instructions can use.


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:224
+    (instregex "^MUL(H|L)(I|W|D)(8)?(U|O)?(_rec)?$"),
+    ISEL, ISEL8, MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>;
+
----------------
Seems I can not find `mflr`, is it expected?


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:244
+    LBARX, LBARXL, LBEPX, LBZCIX, LDARX, LDARXL, LDBRX, LDCIX, LFDEPX, LHARX, LHARXL, LHBRX, LXSIWAX,
+    LHBRX8, LHEPX, LHZCIX, LMW, LSWI, LVSL, LVSR, LWARX, LWARXL, LWBRX, LWBRX8, LWEPX, LWZCIX)>;
+
----------------
```
lswi lswx stswi stswx (unaligned)
LSU,LU
```

```
lwarx ldarx
LSU or LU
```


Repository:
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  https://reviews.llvm.org/D154488/new/

https://reviews.llvm.org/D154488