[PATCH] D159399: [RISCV] Only emit .option when extension is supported

[Piyou Chen via Phabricator via llvm-commits]

BeMg updated this revision to Diff 555668.
BeMg added a comment.

Rename NeedEmitOptionArch with EmittedOptionArch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159399/new/

https://reviews.llvm.org/D159399

Files:
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll


Index: llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
===================================================================
--- llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
+++ llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
@@ -35,10 +35,10 @@
   ret void
 }
 
-; CHECK: .option push
+; CHECK-NOT: .option push
 define void @test5() "target-features"="+unaligned-scalar-mem" {
 ; CHECK-LABEL: test5
-; CHECK: .option pop
+; CHECK-NOT: .option pop
 entry:
   ret void
 }
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -88,8 +88,7 @@
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
-  void emitDirectiveOptionArch();
-  bool isSameAttribute();
+  bool emitDirectiveOptionArch();
 
 private:
   void emitAttributes();
@@ -252,7 +251,7 @@
   return false;
 }
 
-void RISCVAsmPrinter::emitDirectiveOptionArch() {
+bool RISCVAsmPrinter::emitDirectiveOptionArch() {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   SmallVector<RISCVOptionArchArg> NeedEmitStdOptionArgs;
@@ -268,28 +267,26 @@
                                                 : RISCVOptionArchArgType::Minus;
     NeedEmitStdOptionArgs.emplace_back(Delta, Feature.Key);
   }
-  if (!NeedEmitStdOptionArgs.empty())
+  if (!NeedEmitStdOptionArgs.empty()) {
+    RTS.emitDirectiveOptionPush();
     RTS.emitDirectiveOptionArch(NeedEmitStdOptionArgs);
-}
+    return true;
+  }
 
-bool RISCVAsmPrinter::isSameAttribute() {
-  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
-  return MCSTI.getFeatureBits() == STI->getFeatureBits();
+  return false;
 }
 
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget<RISCVSubtarget>();
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
-  if (!isSameAttribute()) {
-    RTS.emitDirectiveOptionPush();
-    emitDirectiveOptionArch();
-  }
+
+  bool EmittedOptionArch = emitDirectiveOptionArch();
 
   SetupMachineFunction(MF);
   emitFunctionBody();
 
-  if (!isSameAttribute())
+  if (EmittedOptionArch)
     RTS.emitDirectiveOptionPop();
   return false;
 }


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