[llvm] 1c43aa4 - [RISCV] Kill off redundant field XLenVT [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 31 11:20:21 PDT 2023
Author: Philip Reames
Date: 2023-08-31T11:20:06-07:00
New Revision: 1c43aa44d8bb7c62fb8ae703e671367a54a37da5
URL: https://github.com/llvm/llvm-project/commit/1c43aa44d8bb7c62fb8ae703e671367a54a37da5
DIFF: https://github.com/llvm/llvm-project/commit/1c43aa44d8bb7c62fb8ae703e671367a54a37da5.diff
LOG: [RISCV] Kill off redundant field XLenVT [nfc]
We're already tracking XLen, we can compute XLenVt from that. Note that XLen itself should probably be driven from IsRV64 (the processor flag), but I'm leaving that to a separate change (with review).
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index c2d42817088303..bd43981a8ae44a 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -66,10 +66,8 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
TuneCPU = CPU;
ParseSubtargetFeatures(CPU, TuneCPU, FS);
- if (Is64Bit) {
- XLenVT = MVT::i64;
+ if (Is64Bit)
XLen = 64;
- }
TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
RISCVFeatures::validate(TT, getFeatureBits());
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 7d3ff437bd79e0..bfc68774f50612 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,7 +50,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned XLen = 32;
unsigned ZvlLen = 0;
- MVT XLenVT = MVT::i32;
unsigned RVVVectorBitsMin;
unsigned RVVVectorBitsMax;
uint8_t MaxInterleaveFactor = 2;
@@ -127,8 +126,14 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
}
bool is64Bit() const { return IsRV64; }
- MVT getXLenVT() const { return XLenVT; }
- unsigned getXLen() const { return XLen; }
+ MVT getXLenVT() const {
+ return MVT::getIntegerVT(getXLen());
+ }
+ unsigned getXLen() const {
+ assert((XLen == 32 || XLen == 64) &&
+ "unexpected xlen");
+ return XLen;
+ }
unsigned getFLen() const {
if (HasStdExtD)
return 64;
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