[llvm] d1c3784 - [RISCV] Prefer ShortForwardBranch over the fully generic Zicond expansion.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-08-31T11:07:35-07:00
New Revision: d1c3784adfb54594fd1d6b3f76aac017099f21a5

URL: https://github.com/llvm/llvm-project/commit/d1c3784adfb54594fd1d6b3f76aac017099f21a5
DIFF: https://github.com/llvm/llvm-project/commit/d1c3784adfb54594fd1d6b3f76aac017099f21a5.diff

LOG: [RISCV] Prefer ShortForwardBranch over the fully generic Zicond expansion.

Short forward branch is shorter than (or (czero.eqz), (czero.nez)).

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D159295

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6a4995ea96b26d..959935ff0bd56a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6582,9 +6582,12 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
       return V;
 
     // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
-    return DAG.getNode(ISD::OR, DL, VT,
-                       DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
-                       DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, CondV));
+    // Unless we have the short forward branch optimization.
+    if (!Subtarget.hasShortForwardBranchOpt())
+      return DAG.getNode(
+          ISD::OR, DL, VT,
+          DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
+          DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, CondV));
   }
 
   if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))

diff  --git a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
index c239acc7f3f48e..862c366b553f87 100644
--- a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
+++ b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
@@ -2,7 +2,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=NOSFB %s
 ; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=SFB %s
+; RUN:   | FileCheck -check-prefixes=SFB,NOZICOND %s
+; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond \
+; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s
 
 ; The sifive-7-series can predicate a mv.
 
@@ -91,13 +93,18 @@ define signext i32 @test4(i32 signext %x, i32 signext %z) {
 ; NOSFB-NEXT:    and a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
-; SFB-LABEL: test4:
-; SFB:       # %bb.0:
-; SFB-NEXT:    beqz a1, .LBB3_2
-; SFB-NEXT:  # %bb.1:
-; SFB-NEXT:    li a0, 0
-; SFB-NEXT:  .LBB3_2:
-; SFB-NEXT:    ret
+; NOZICOND-LABEL: test4:
+; NOZICOND:       # %bb.0:
+; NOZICOND-NEXT:    beqz a1, .LBB3_2
+; NOZICOND-NEXT:  # %bb.1:
+; NOZICOND-NEXT:    li a0, 0
+; NOZICOND-NEXT:  .LBB3_2:
+; NOZICOND-NEXT:    ret
+;
+; ZICOND-LABEL: test4:
+; ZICOND:       # %bb.0:
+; ZICOND-NEXT:    czero.nez a0, a0, a1
+; ZICOND-NEXT:    ret
   %c = icmp eq i32 %z, 0
   %b = select i1 %c, i32 %x, i32 0
   ret i32 %b
@@ -112,13 +119,18 @@ define signext i32 @test5(i32 signext %x, i32 signext %z) {
 ; NOSFB-NEXT:    and a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
-; SFB-LABEL: test5:
-; SFB:       # %bb.0:
-; SFB-NEXT:    bnez a1, .LBB4_2
-; SFB-NEXT:  # %bb.1:
-; SFB-NEXT:    li a0, 0
-; SFB-NEXT:  .LBB4_2:
-; SFB-NEXT:    ret
+; NOZICOND-LABEL: test5:
+; NOZICOND:       # %bb.0:
+; NOZICOND-NEXT:    bnez a1, .LBB4_2
+; NOZICOND-NEXT:  # %bb.1:
+; NOZICOND-NEXT:    li a0, 0
+; NOZICOND-NEXT:  .LBB4_2:
+; NOZICOND-NEXT:    ret
+;
+; ZICOND-LABEL: test5:
+; ZICOND:       # %bb.0:
+; ZICOND-NEXT:    czero.eqz a0, a0, a1
+; ZICOND-NEXT:    ret
   %c = icmp eq i32 %z, 0
   %b = select i1 %c, i32 0, i32 %x
   ret i32 %b