[PATCH] D159253: [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 31 10:31:32 PDT 2023

craig.topper added a comment.

In D159253#4631902 <https://reviews.llvm.org/D159253#4631902>, @reames wrote:

> Mostly for completeness sake, here's how I convinced myself this is correct.
> - If we could generate a unsigned 32 constant in the 64 bit register, we could do OR((shl C, 32), C).  The ADD and OR are equivalent in this case due to no common set bits.
> - Generating a zext(i32) is hard, but we can generate a sext(i32) and then truncate.  We then have to put the zext/trunc somewhere.
> - add.uw applies a trunc/zext operation to one input.
> A couple of thoughts off that.
> - It would be super handy to have a sh32add.uw.  To bad we don't.
> - shl.uw allows us to produce a 32 bit contiguous constant at any point in the i64.
> - sh3add.uw allows us to produce a 35 bit constant or a sign extended 35 bit constant in at most four instructions.

I think sh32add.uw is equivalent to the PACK instruction from the old Zbp spec which took the lower 32 bits from two registers and concatenated them.
Did you mean slli.uw instead of shl.uw?

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