[PATCH] D159253: [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.

LGTM.

Mostly for completeness sake, here's how I convinced myself this is correct.

- If we could generate a unsigned 32 constant in the 64 bit register, we could do OR((shl C, 32), C).  The ADD and OR are equivalent in this case due to no common set bits.
- Generating a zext(i32) is hard, but we can generate a sext(i32) and then truncate.  We then have to put the zext/trunc somewhere.
- add.uw applies a trunc/zext operation to one input.

A couple of thoughts off that.

- It would be super handy to have a sh32add.uw.  To bad we don't.
- shl.uw allows us to produce a 32 bit contiguous constant at any point in the i64.
- sh3add.uw allows us to produce a 35 bit constant or a sign extended 35 bit constant in at most four instructions.


Repository:
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https://reviews.llvm.org/D159253