[PATCH] D159230: [RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2959
 static SDValue findVSplat(SDValue N) {
+  while (N.getOpcode() == ISD::INSERT_SUBVECTOR) {
+    if (!N.getOperand(0).isUndef())
----------------
Are we getting multiple nested insert_subvectors? If their vector operands are undef shouldn't they be getting combined away? I found this combine in DAGCombiner.cpp:

```
  // Eliminate an intermediate insert into an undef vector:
  // insert_subvector undef, (insert_subvector undef, X, 0), N2 -->
  // insert_subvector undef, X, N2
  if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
      N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)))
    return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
                       N1.getOperand(1), N2);
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D159230/new/

https://reviews.llvm.org/D159230