[PATCH] D159215: [RISCV] Fix crash during during i1 vector bitreverse lowering

[Luke Lau via Phabricator via llvm-commits]

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A shuffle of v256i1 with a large enough minimum vlen might make it through type
legalization and into lowering. In this case, zvl1024b was enough. The
bitreverse shuffle lowering would then try to convert this to a v1i256 type
which is invalid (v1i128 exists though, which is why the existing v128i1 tests
were fine).

This patch checks to make sure that the new type is not only legal but also
valid.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159215

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

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