[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp:66
+      // FIXME: Remove the following check after D158759 to handle
+      // PseudoVSETVLI/PseudoVSETIVLI
+      if (MI.isPseudo())
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I cannot handle `PseudoVSETVLI/PseudoVSETIVLI` now since the diff is too large (about 300+ KLOCs with full context).
Could I remove this check after committing this patch?



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12396
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
-; RV64ZVE32F-NEXT:    li a3, 32
+; RV64ZVE32F-NEXT:    li zero, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
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I don't know why DCE does not remove this dead instruction.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158759/new/

https://reviews.llvm.org/D158759