[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused
Yingwei Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 30 00:19:08 PDT 2023
dtcxzyw updated this revision to Diff 554599.
dtcxzyw retitled this revision from "[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused" to "[RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused".
dtcxzyw edited the summary of this revision.
dtcxzyw added a comment.
- Rebase
- Handle computational instrs
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158759/new/
https://reviews.llvm.org/D158759
Files:
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
llvm/test/CodeGen/RISCV/branch.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/half-mem.ll
llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
llvm/test/CodeGen/RISCV/mem.ll
llvm/test/CodeGen/RISCV/mem64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
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