[PATCH] D159053: [RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:13908
+    // to fp_round(vf32 splat_vector (s)). But the constant fold of getNode
+    // would fold fp_round(vf32 splat_vector (0)) to vf16 splat_vector (0)
+    // again, so we should early lower splat_vector (fp16 0) to vmv.v.i before
----------------
What prevents this for constants that aren't 0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159053/new/

https://reviews.llvm.org/D159053