[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb
Yingwei Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 26 10:55:49 PDT 2023
dtcxzyw updated this revision to Diff 553748.
dtcxzyw removed a reviewer: RKSimon.
dtcxzyw added a comment.
- Rebase
- Add fixed-length vector tests
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D156390/new/
https://reviews.llvm.org/D156390
Files:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rv32zbb.ll
llvm/test/CodeGen/RISCV/rv64zbb.ll
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
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